/* system.h * * Machine generated for a CPU named "cpu_0" as defined in: * d:\GX_CIDE_SOPC\EP3C80\projects\cide_7f\software\syslib\..\..\nios2_7f.ptf * * Generated: 2008-09-08 14:32:49.437 * */#ifndef __SYSTEM_H_#define __SYSTEM_H_/*DO NOT MODIFY THIS FILE   Changing this file will have subtle consequences   which will almost certainly lead to a nonfunctioning   system. If you do modify this file, be aware that your   changes will be overwritten and lost when this file   is generated again.DO NOT MODIFY THIS FILE*//*******************************************************************************                                                                             ** License Agreement                                                           **                                                                             ** Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           ** All rights reserved.                                                        **                                                                             ** Permission is hereby granted, free of charge, to any person obtaining a     ** copy of this software and associated documentation files (the "Software"),  ** to deal in the Software without restriction, including without limitation   ** the rights to use, copy, modify, merge, publish, distribute, sublicense,    ** and/or sell copies of the Software, and to permit persons to whom the       ** Software is furnished to do so, subject to the following conditions:        **                                                                             ** The above copyright notice and this permission notice shall be included in  ** all copies or substantial portions of the Software.                         **                                                                             ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  ** IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    ** FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ** AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      ** LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     ** FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         ** DEALINGS IN THE SOFTWARE.                                                   **                                                                             ** This agreement shall be governed in all respects by the laws of the State   ** of California and by the laws of the United States of America.              **                                                                             *******************************************************************************//* * system configuration * */#define ALT_SYSTEM_NAME "nios2_7f"#define ALT_CPU_NAME "cpu_0"#define ALT_CPU_ARCHITECTURE "altera_nios2"#define ALT_DEVICE_FAMILY "CYCLONEIII"#define ALT_STDIN "/dev/jtag_uart_0"#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"#define ALT_STDIN_BASE 0x01503080#define ALT_STDIN_DEV jtag_uart_0#define ALT_STDIN_PRESENT#define ALT_STDOUT "/dev/jtag_uart_0"#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"#define ALT_STDOUT_BASE 0x01503080#define ALT_STDOUT_DEV jtag_uart_0#define ALT_STDOUT_PRESENT#define ALT_STDERR "/dev/jtag_uart_0"#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"#define ALT_STDERR_BASE 0x01503080#define ALT_STDERR_DEV jtag_uart_0#define ALT_STDERR_PRESENT#define ALT_CPU_FREQ 50000000#define ALT_IRQ_BASE NULL/* * processor configuration * */#define NIOS2_CPU_IMPLEMENTATION "small"#define NIOS2_BIG_ENDIAN 0#define NIOS2_ICACHE_SIZE 4096#define NIOS2_DCACHE_SIZE 0#define NIOS2_ICACHE_LINE_SIZE 32#define NIOS2_ICACHE_LINE_SIZE_LOG2 5#define NIOS2_DCACHE_LINE_SIZE 0#define NIOS2_DCACHE_LINE_SIZE_LOG2 0#define NIOS2_FLUSHDA_SUPPORTED#define NIOS2_EXCEPTION_ADDR 0x00800020#define NIOS2_RESET_ADDR 0x01200000#define NIOS2_BREAK_ADDR 0x01501820#define NIOS2_HAS_DEBUG_STUB#define NIOS2_CPU_ID_SIZE 1#define NIOS2_CPU_ID_VALUE 0/* * A define for each class of peripheral * */#define __ALTERA_AVALON_JTAG_UART#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER#define __ALTERA_AVALON_PIO#define __ALTERA_AVALON_TIMER#define __ALTERA_AVALON_SYSID#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER#define __ALTERA_AVALON_ONCHIP_MEMORY2#define __ALTERA_AVALON_TRI_STATE_BRIDGE#define __ALTERA_AVALON_CFI_FLASH#define __ALTERA_AVALON_CF#define __GX_SRAM_256_16/* * jtag_uart_0 configuration * */#define JTAG_UART_0_NAME "/dev/jtag_uart_0"#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"#define JTAG_UART_0_BASE 0x01503080#define JTAG_UART_0_SPAN 8#define JTAG_UART_0_IRQ 0#define JTAG_UART_0_WRITE_DEPTH 64#define JTAG_UART_0_READ_DEPTH 64#define JTAG_UART_0_WRITE_THRESHOLD 8#define JTAG_UART_0_READ_THRESHOLD 8#define JTAG_UART_0_READ_CHAR_STREAM ""#define JTAG_UART_0_SHOWASCII 1#define JTAG_UART_0_READ_LE 0#define JTAG_UART_0_WRITE_LE 0#define JTAG_UART_0_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart/* * sdram_0 configuration * */#define SDRAM_0_NAME "/dev/sdram_0"#define SDRAM_0_TYPE "altera_avalon_new_sdram_controller"#define SDRAM_0_BASE 0x00800000#define SDRAM_0_SPAN 8388608#define SDRAM_0_REGISTER_DATA_IN 1#define SDRAM_0_SIM_MODEL_BASE 1#define SDRAM_0_SDRAM_DATA_WIDTH 16#define SDRAM_0_SDRAM_ADDR_WIDTH 12#define SDRAM_0_SDRAM_ROW_WIDTH 12#define SDRAM_0_SDRAM_COL_WIDTH 8#define SDRAM_0_SDRAM_NUM_CHIPSELECTS 1#define SDRAM_0_SDRAM_NUM_BANKS 4#define SDRAM_0_REFRESH_PERIOD 15.625#define SDRAM_0_POWERUP_DELAY 100.0#define SDRAM_0_CAS_LATENCY 3#define SDRAM_0_T_RFC 70.0#define SDRAM_0_T_RP 20.0#define SDRAM_0_T_MRD 3#define SDRAM_0_T_RCD 20.0#define SDRAM_0_T_AC 5.5#define SDRAM_0_T_WR 14.0#define SDRAM_0_INIT_REFRESH_COMMANDS 2#define SDRAM_0_INIT_NOP_DELAY 0.0#define SDRAM_0_SHARED_DATA 0#define SDRAM_0_SDRAM_BANK_WIDTH 2#define SDRAM_0_TRISTATE_BRIDGE_SLAVE ""#define SDRAM_0_STARVATION_INDICATOR 0#define SDRAM_0_IS_INITIALIZED 1#define ALT_MODULE_CLASS_sdram_0 altera_avalon_new_sdram_controller/* * led_pio configuration * */#define LED_PIO_NAME "/dev/led_pio"#define LED_PIO_TYPE "altera_avalon_pio"#define LED_PIO_BASE 0x01503060#define LED_PIO_SPAN 16#define LED_PIO_DO_TEST_BENCH_WIRING 0#define LED_PIO_DRIVEN_SIM_VALUE 0#define LED_PIO_HAS_TRI 0#define LED_PIO_HAS_OUT 1#define LED_PIO_HAS_IN 0#define LED_PIO_CAPTURE 0#define LED_PIO_DATA_WIDTH 8#define LED_PIO_RESET_VALUE 0#define LED_PIO_EDGE_TYPE "NONE"#define LED_PIO_IRQ_TYPE "NONE"#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0#define LED_PIO_FREQ 50000000#define ALT_MODULE_CLASS_led_pio altera_avalon_pio/* * timer_0 configuration * */#define TIMER_0_NAME "/dev/timer_0"#define TIMER_0_TYPE "altera_avalon_timer"#define TIMER_0_BASE 0x01503040#define TIMER_0_SPAN 32#define TIMER_0_IRQ 1#define TIMER_0_ALWAYS_RUN 0#define TIMER_0_FIXED_PERIOD 0#define TIMER_0_SNAPSHOT 1#define TIMER_0_PERIOD 20#define TIMER_0_PERIOD_UNITS "ms"#define TIMER_0_RESET_OUTPUT 0#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0#define TIMER_0_LOAD_VALUE 999999#define TIMER_0_COUNTER_SIZE 32#define TIMER_0_MULT 0.0010#define TIMER_0_TICKS_PER_SEC 50#define TIMER_0_FREQ 50000000#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer/* * sysid configuration * */#define SYSID_NAME "/dev/sysid"#define SYSID_TYPE "altera_avalon_sysid"#define SYSID_BASE 0x01503088#define SYSID_SPAN 8#define SYSID_ID 922251475u#define SYSID_TIMESTAMP 1220854184u#define SYSID_REGENERATE_VALUES 0#define ALT_MODULE_CLASS_sysid altera_avalon_sysid/* * epcs_controller configuration * */#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"#define EPCS_CONTROLLER_BASE 0x01502000#define EPCS_CONTROLLER_SPAN 2048#define EPCS_CONTROLLER_IRQ 2#define EPCS_CONTROLLER_DATABITS 8#define EPCS_CONTROLLER_TARGETCLOCK 20#define EPCS_CONTROLLER_CLOCKUNITS "MHz"#define EPCS_CONTROLLER_CLOCKMULT 1000000#define EPCS_CONTROLLER_NUMSLAVES 1#define EPCS_CONTROLLER_ISMASTER 1#define EPCS_CONTROLLER_CLOCKPOLARITY 0#define EPCS_CONTROLLER_CLOCKPHASE 0#define EPCS_CONTROLLER_LSBFIRST 0#define EPCS_CONTROLLER_EXTRADELAY 0#define EPCS_CONTROLLER_TARGETSSDELAY 100#define EPCS_CONTROLLER_DELAYUNITS "us"#define EPCS_CONTROLLER_DELAYMULT "1e-006"#define EPCS_CONTROLLER_PREFIX "epcs_"#define EPCS_CONTROLLER_REGISTER_OFFSET 0x400#define EPCS_CONTROLLER_USE_ASMI_ATOM 0#define EPCS_CONTROLLER_CLOCKUNIT "kHz"#define EPCS_CONTROLLER_DELAYUNIT "us"#define ALT_MODULE_CLASS_epcs_controller altera_avalon_epcs_flash_controller/* * onchip_memory_0 configuration * */#define ONCHIP_MEMORY_0_NAME "/dev/onchip_memory_0"#define ONCHIP_MEMORY_0_TYPE "altera_avalon_onchip_memory2"#define ONCHIP_MEMORY_0_BASE 0x01502800#define ONCHIP_MEMORY_0_SPAN 2048#define ONCHIP_MEMORY_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0#define ONCHIP_MEMORY_0_RAM_BLOCK_TYPE "AUTO"#define ONCHIP_MEMORY_0_INIT_CONTENTS_FILE "onchip_memory_0"#define ONCHIP_MEMORY_0_NON_DEFAULT_INIT_FILE_ENABLED 0#define ONCHIP_MEMORY_0_GUI_RAM_BLOCK_TYPE "Automatic"#define ONCHIP_MEMORY_0_WRITEABLE 1#define ONCHIP_MEMORY_0_DUAL_PORT 0#define ONCHIP_MEMORY_0_SIZE_VALUE 2048#define ONCHIP_MEMORY_0_SIZE_MULTIPLE 1#define ONCHIP_MEMORY_0_USE_SHALLOW_MEM_BLOCKS 0#define ONCHIP_MEMORY_0_INIT_MEM_CONTENT 1#define ONCHIP_MEMORY_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0#define ONCHIP_MEMORY_0_INSTANCE_ID "NONE"#define ONCHIP_MEMORY_0_READ_DURING_WRITE_MODE "DONT_CARE"#define ONCHIP_MEMORY_0_IGNORE_AUTO_BLOCK_TYPE_ASSIGNMENT 1#define ONCHIP_MEMORY_0_CONTENTS_INFO "QUARTUS_PROJECT_DIR/onchip_memory_0.hex 1220854486"#define ALT_MODULE_CLASS_onchip_memory_0 altera_avalon_onchip_memory2/* * ext_bus configuration * */#define EXT_BUS_NAME "/dev/ext_bus"#define EXT_BUS_TYPE "altera_avalon_tri_state_bridge"#define ALT_MODULE_CLASS_ext_bus altera_avalon_tri_state_bridge/* * cfi_flash_0 configuration * */#define CFI_FLASH_0_NAME "/dev/cfi_flash_0"#define CFI_FLASH_0_TYPE "altera_avalon_cfi_flash"#define CFI_FLASH_0_BASE 0x01200000#define CFI_FLASH_0_SPAN 2097152#define CFI_FLASH_0_SETUP_VALUE 40#define CFI_FLASH_0_WAIT_VALUE 160#define CFI_FLASH_0_HOLD_VALUE 40#define CFI_FLASH_0_TIMING_UNITS "ns"#define CFI_FLASH_0_UNIT_MULTIPLIER 1#define CFI_FLASH_0_SIZE 2097152#define ALT_MODULE_CLASS_cfi_flash_0 altera_avalon_cfi_flash/* * cf/ctl configuration * */#define CF_CTL_NAME "/dev/cf"#define CF_CTL_TYPE "altera_avalon_cf"#define CF_CTL_BASE 0x01503070#define CF_CTL_SPAN 16#define CF_CTL_IRQ 3#define ALT_MODULE_CLASS_cf altera_avalon_cf/* * cf/ide configuration * */#define CF_IDE_NAME "/dev/cf"#define CF_IDE_TYPE "altera_avalon_cf"#define CF_IDE_BASE 0x01503000#define CF_IDE_SPAN 64#define CF_IDE_IRQ 4#define ALT_MODULE_CLASS_cf altera_avalon_cf/* * sram configuration * */#define SRAM_NAME "/dev/sram"#define SRAM_TYPE "gx_sram_256_16"#define SRAM_BASE 0x01480000#define SRAM_SPAN 524288#define SRAM_TERMINATED_PORTS ""#define ALT_MODULE_CLASS_sram gx_sram_256_16/* * system library configuration * */#define ALT_MAX_FD 32#define ALT_SYS_CLK TIMER_0#define ALT_TIMESTAMP_CLK none/* * Devices associated with code sections. * */#define ALT_TEXT_DEVICE       SDRAM_0#define ALT_RODATA_DEVICE     SDRAM_0#define ALT_RWDATA_DEVICE     SDRAM_0#define ALT_EXCEPTIONS_DEVICE SDRAM_0#define ALT_RESET_DEVICE      CFI_FLASH_0#endif /* __SYSTEM_H_ */