+------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------+
; ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32           ; 8            ; 32           ; 8            ; yes                    ; no                      ; yes                    ; no                      ; 256  ; 32                          ; 8                           ; 32                          ; 8                           ; 256                 ; 1    ; None ; M4K_X13_Y8 ;
+------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.


+-----------------------------------------------------+
; Interconnect Usage Summary                          ;
+----------------------------+------------------------+
; Interconnect Resource Type ; Usage                  ;
+----------------------------+------------------------+
; C4s                        ; 45 / 8,840 ( < 1 % )   ;
; Direct links               ; 21 / 11,506 ( < 1 % )  ;
; Global clocks              ; 4 / 8 ( 50 % )         ;
; LAB clocks                 ; 14 / 156 ( 9 % )       ;
; LUT chains                 ; 2 / 2,619 ( < 1 % )    ;
; Local interconnects        ; 106 / 11,506 ( < 1 % ) ;
; M4K buffers                ; 8 / 468 ( 2 % )        ;
; R4s                        ; 44 / 7,520 ( < 1 % )   ;
+----------------------------+------------------------+


+---------------------------------------------------------------------------+
; LAB Logic Elements                                                        ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements  (Average = 7.93) ; Number of LABs  (Total = 14) ;
+--------------------------------------------+------------------------------+
; 1                                          ; 2                            ;
; 2                                          ; 0                            ;
; 3                                          ; 0                            ;
; 4                                          ; 0                            ;
; 5                                          ; 1                            ;
; 6                                          ; 0                            ;
; 7                                          ; 2                            ;
; 8                                          ; 0                            ;
; 9                                          ; 0                            ;
; 10                                         ; 9                            ;
+--------------------------------------------+------------------------------+


+-------------------------------------------------------------------+
; LAB-wide Signals                                                  ;
+------------------------------------+------------------------------+
; LAB-wide Signals  (Average = 2.50) ; Number of LABs  (Total = 14) ;
+------------------------------------+------------------------------+
; 1 Async. clear                     ; 14                           ;
; 1 Clock                            ; 14                           ;
; 1 Clock enable                     ; 2                            ;
; 1 Sync. clear                      ; 3                            ;
; 2 Clock enables                    ; 2                            ;
+------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Signals Sourced                                                        ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 8.07) ; Number of LABs  (Total = 14) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 2                            ;
; 2                                           ; 0                            ;
; 3                                           ; 0                            ;
; 4                                           ; 0                            ;
; 5                                           ; 1                            ;
; 6                                           ; 0                            ;
; 7                                           ; 2                            ;
; 8                                           ; 0                            ;
; 9                                           ; 0                            ;
; 10                                          ; 7                            ;
; 11                                          ; 2                            ;
+---------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 5.07) ; Number of LABs  (Total = 14) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 0                            ;
; 1                                               ; 2                            ;
; 2                                               ; 0                            ;
; 3                                               ; 1                            ;
; 4                                               ; 1                            ;
; 5                                               ; 4                            ;
; 6                                               ; 3                            ;
; 7                                               ; 1                            ;
; 8                                               ; 1                            ;
; 9                                               ; 1                            ;
+-------------------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                        ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 7.64) ; Number of LABs  (Total = 14) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 0                            ;
; 2                                           ; 0                            ;
; 3                                           ; 3                            ;
; 4                                           ; 0                            ;
; 5                                           ; 1                            ;
; 6                                           ; 1                            ;
; 7                                           ; 2                            ;
; 8                                           ; 2                            ;
; 9                                           ; 1                            ;
; 10                                          ; 1                            ;
; 11                                          ; 0                            ;
; 12                                          ; 2                            ;
; 13                                          ; 0                            ;
; 14                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Active Serial       ;
; Error detection CRC