; Worst-case tsu               ; N/A                                      ; None          ; 4.936 ns                         ; rxd                                                                                                     ; rx:rx1|read_en                                                                                          ; --         ; clk32    ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 7.609 ns                         ; tx:tx1|txd                                                                                              ; txd                                                                                                     ; clk32      ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; -4.575 ns                        ; rxd                                                                                                     ; rx:rx1|data_reg[9]                                                                                      ; --         ; clk32    ; 0            ;
; Clock Setup: 'clk32'         ; N/A                                      ; None          ; 88.25 MHz ( period = 11.332 ns ) ; ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 ; tx:tx1|data_reg[8]                                                                                      ; clk32      ; clk32    ; 0            ;
; Clock Hold: 'clk32'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; raddr[4]                                                                                                ; ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 ; clk32      ; clk32    ; 18           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                                                         ;                                                                                                         ;            ;          ; 18           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk32           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+