library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity tx is

port(clk32,wclk,rstn,wen:in std_logic;
     txd_data:in std_logic_vector(7 downto 0);
     write_en,write_end,txd:out std_logic  --------一幀數據接收標志
     );
end tx;

architecture behav2 of tx is	
type states is(txd_start,txd_wait);--------數據總線狀態	
signal state1:states:=txd_wait;
signal data_reg:std_logic_vector(10 downto 0);

begin
--------------------------------------------------------------------
 process(clk32,rstn)
    begin
       if(rstn='0')then
          txd<='1';
          write_en<='0';
          write_end<='0';
          state1<=txd_wait;
          data_reg<="00000000000";
       elsif(clk32'event and clk32='1')then
          case state1 is
            when txd_wait=>
               if (wen='1')then
                  write_en<='1';
                  write_end<='0';
                  state1<=txd_start;
                  data_reg(10 downto 0)<="11"&txd_data(7 downto 0)&'0';
               else
                  write_en<='0';
                  write_end<='0';
                  state1<=txd_wait;
               end if;
            when txd_start=>
               write_en<='0';
               if (wclk = '1')then
                  txd<=data_reg(0);
                  data_reg<="0"&data_reg(10 downto 1);
                  write_end<='0';
               else
                  if (data_reg=0)then
                     write_end<='1';
                     state1<=txd_wait;
                  else
                     state1<=txd_start;
                  end if;
               end if;
             when others =>
                state1 <= txd_wait;
          end case;
       end if;
 end process;
---------------------------------------------------------------------------
end behav2;