library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity rx is

port(clk32,rclk,rstn,rxd:in std_logic;
     rxd_data:out std_logic_vector(7 downto 0);
     read_en,read_end:out std_logic  --------一幀數據接收標志
     );
end rx;

architecture behav1 of rx is	
type states is(rxd_start,rxd_wait);--------數據總線狀態	
signal state1:states:=rxd_wait;
signal data_reg:std_logic_vector(9 downto 0);
signal r_end:std_logic;
begin
---------------------------------------------------------------------
 process(clk32,rstn)
    begin
       if(rstn='0')then
          read_en<='0';
          read_end<='0';
          r_end<='0';
          state1<=rxd_wait;
          rxd_data<="00000000";
          data_reg<="1111111111";
       elsif(clk32'event and clk32='1')then
          read_end<=r_end;
          case state1 is
            when rxd_wait=>
               if (rxd='0')then
                  read_en<='1';
                  r_end<='0';
                  state1<=rxd_start;
               else
                  read_en<='0';
                  r_end<='0';
                  state1<=rxd_wait;
               end if;
            when rxd_start=>
               read_en<='0';
               if (rclk = '1')then
                  data_reg<=rxd&data_reg(9 downto 1);
                  r_end<='0';
               else
                  if (data_reg(0)='0')then
                     r_end<='1';
                     data_reg<="1111111111";
                     rxd_data<=data_reg(8 downto 1);
                     state1<=rxd_wait;
                  else
                     state1<=rxd_start;
                  end if;
               end if;
             when others =>
                state1 <= rxd_wait;
          end case;
       end if;
 end process;
---------------------------------------------------------------------
end behav1;