{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk32 memory ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg0 register tx:tx1\|data_reg\[8\] 88.25 MHz 11.332 ns Internal " "Info: Clock \"clk32\" has Internal fmax of 88.25 MHz between source memory \"ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg0\" and destination register \"tx:tx1\|data_reg\[8\]\" (period= 11.332 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.724 ns + Longest memory register " "Info: + Longest memory to register delay is 5.724 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg0 1 MEM M4K_X13_Y8 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y8; Fanout = 8; MEM Node = 'ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_06h1.tdf" "" { Text "F:/FPGA/feng_rs0/db/altsyncram_06h1.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.317 ns) 4.317 ns ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|q_b\[7\] 2 MEM M4K_X13_Y8 1 " "Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|q_b\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.317 ns" { ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|q_b[7] } "NODE_NAME" } } { "db/altsyncram_06h1.tdf" "" { Text "F:/FPGA/feng_rs0/db/altsyncram_06h1.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.098 ns) + CELL(0.309 ns) 5.724 ns tx:tx1\|data_reg\[8\] 3 REG LC_X16_Y8_N9 2 " "Info: 3: + IC(1.098 ns) + CELL(0.309 ns) = 5.724 ns; Loc. = LC_X16_Y8_N9; Fanout = 2; REG Node = 'tx:tx1\|data_reg\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.407 ns" { ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|q_b[7] tx:tx1|data_reg[8] } "NODE_NAME" } } { "tx.vhd" "" { Text "F:/FPGA/feng_rs0/tx.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.626 ns ( 80.82 % ) " "Info: Total cell delay = 4.626 ns ( 80.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.098 ns ( 19.18 % ) " "Info: Total interconnect delay = 1.098 ns ( 19.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.724 ns" { ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|q_b[7] tx:tx1|data_reg[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.724 ns" { ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|q_b[7] tx:tx1|data_reg[8] } { 0.000ns 0.000ns 1.098ns } { 0.000ns 4.317ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.921 ns - Smallest " "Info: - Smallest clock skew is -4.921 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk32 destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clk32\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk32 1 CLK PIN_16 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 82; CLK Node = 'clk32'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk32 } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns tx:tx1\|data_reg\[8\] 2 REG LC_X16_Y8_N9 2 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X16_Y8_N9; Fanout = 2; REG Node = 'tx:tx1\|data_reg\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk32 tx:tx1|data_reg[8] } "NODE_NAME" } } { "tx.vhd" "" { Text "F:/FPGA/feng_rs0/tx.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk32 tx:tx1|data_reg[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk32 clk32~out0 tx:tx1|data_reg[8] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk32 source 7.703 ns - Longest memory " "Info: - Longest clock path from clock \"clk32\" to source memory is 7.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk32 1 CLK PIN_16 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 82; CLK Node = 'clk32'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk32 } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns ram_rclk 2 REG LC_X8_Y8_N4 11 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y8_N4; Fanout = 11; REG Node = 'ram_rclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.495 ns" { clk32 ram_rclk } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.021 ns) + CELL(0.718 ns) 7.703 ns ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M4K_X13_Y8 8 " "Info: 3: + IC(4.021 ns) + CELL(0.718 ns) = 7.703 ns; Loc. = M4K_X13_Y8; Fanout = 8; MEM Node = 'ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.739 ns" { ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_06h1.tdf" "" { Text "F:/FPGA/feng_rs0/db/altsyncram_06h1.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.122 ns ( 40.53 % ) " "Info: Total cell delay = 3.122 ns ( 40.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns ( 59.47 % ) " "Info: Total interconnect delay = 4.581 ns ( 59.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.703 ns" { clk32 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.703 ns" { clk32 clk32~out0 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.560ns 4.021ns } { 0.000ns 1.469ns 0.935ns 0.718ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk32 tx:tx1|data_reg[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk32 clk32~out0 tx:tx1|data_reg[8] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.703 ns" { clk32 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.703 ns" { clk32 clk32~out0 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.560ns 4.021ns } { 0.000ns 1.469ns 0.935ns 0.718ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_06h1.tdf" "" { Text "F:/FPGA/feng_rs0/db/altsyncram_06h1.tdf" 47 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "tx.vhd" "" { Text "F:/FPGA/feng_rs0/tx.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.724 ns" { ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|q_b[7] tx:tx1|data_reg[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.724 ns" { ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|q_b[7] tx:tx1|data_reg[8] } { 0.000ns 0.000ns 1.098ns } { 0.000ns 4.317ns 0.309ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk32 tx:tx1|data_reg[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk32 clk32~out0 tx:tx1|data_reg[8] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.703 ns" { clk32 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.703 ns" { clk32 clk32~out0 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.560ns 4.021ns } { 0.000ns 1.469ns 0.935ns 0.718ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk32 18 " "Warning: Circuit may not operate. Detected 18 non-operational path(s) clocked by clock \"clk32\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "raddr\[4\] ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg4 clk32 3.029 ns " "Info: Found hold time violation between source  pin or register \"raddr\[4\]\" and destination pin or register \"ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg4\" for clock \"clk32\" (Hold time is 3.029 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.963 ns + Largest " "Info: + Largest clock skew is 4.963 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk32 destination 7.703 ns + Longest memory " "Info: + Longest clock path from clock \"clk32\" to destination memory is 7.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk32 1 CLK PIN_16 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 82; CLK Node = 'clk32'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk32 } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns ram_rclk 2 REG LC_X8_Y8_N4 11 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y8_N4; Fanout = 11; REG Node = 'ram_rclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.495 ns" { clk32 ram_rclk } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.021 ns) + CELL(0.718 ns) 7.703 ns ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg4 3 MEM M4K_X13_Y8 8 " "Info: 3: + IC(4.021 ns) + CELL(0.718 ns) = 7.703 ns; Loc. = M4K_X13_Y8; Fanout = 8; MEM Node = 'ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg4'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.739 ns" { ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } "NODE_NAME" } } { "db/altsyncram_06h1.tdf" "" { Text "F:/FPGA/feng_rs0/db/altsyncram_06h1.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.122 ns ( 40.53 % ) " "Info: Total cell delay = 3.122 ns ( 40.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns ( 59.47 % ) " "Info: Total interconnect delay = 4.581 ns ( 59.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.703 ns" { clk32 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.703 ns" { clk32 clk32~out0 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } { 0.000ns 0.000ns 0.560ns 4.021ns } { 0.000ns 1.469ns 0.935ns 0.718ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk32 source 2.740 ns - Shortest register " "Info: - Shortest clock path from clock \"clk32\" to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk32 1 CLK PIN_16 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 82; CLK Node = 'clk32'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk32 } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns raddr\[4\] 2 REG LC_X12_Y8_N3 2 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; REG Node = 'raddr\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.271 ns" { clk32 raddr[4] } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk32 raddr[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk32 clk32~out0 raddr[4] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.703 ns" { clk32 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.703 ns" { clk32 clk32~out0 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } { 0.000ns 0.000ns 0.560ns 4.021ns } { 0.000ns 1.469ns 0.935ns 0.718ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk32 raddr[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk32 clk32~out0 raddr[4] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 78 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.765 ns - Shortest register memory " "Info: - Shortest register to memory delay is 1.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns raddr\[4\] 1 REG LC_X12_Y8_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; REG Node = 'raddr\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { raddr[4] } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.435 ns) + CELL(0.330 ns) 1.765 ns ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg4 2 MEM M4K_X13_Y8 8 " "Info: 2: + IC(1.435 ns) + CELL(0.330 ns) = 1.765 ns; Loc. = M4K_X13_Y8; Fanout = 8; MEM Node = 'ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\|ram_block1a0~portb_address_reg4'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.765 ns" { raddr[4] ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } "NODE_NAME" } } { "db/altsyncram_06h1.tdf" "" { Text "F:/FPGA/feng_rs0/db/altsyncram_06h1.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.330 ns ( 18.70 % ) " "Info: Total cell delay = 0.330 ns ( 18.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.435 ns ( 81.30 % ) " "Info: Total interconnect delay = 1.435 ns ( 81.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.765 ns" { raddr[4] ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.765 ns" { raddr[4] ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } { 0.000ns 1.435ns } { 0.000ns 0.330ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.055 ns + " "Info: + Micro hold delay of destination is 0.055 ns" {  } { { "db/altsyncram_06h1.tdf" "" { Text "F:/FPGA/feng_rs0/db/altsyncram_06h1.tdf" 47 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.703 ns" { clk32 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.703 ns" { clk32 clk32~out0 ram_rclk ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } { 0.000ns 0.000ns 0.560ns 4.021ns } { 0.000ns 1.469ns 0.935ns 0.718ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk32 raddr[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk32 clk32~out0 raddr[4] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.765 ns" { raddr[4] ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.765 ns" { raddr[4] ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4 } { 0.000ns 1.435ns } { 0.000ns 0.330ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "rx:rx1\|read_en rxd clk32 4.936 ns register " "Info: tsu for register \"rx:rx1\|read_en\" (data pin = \"rxd\", clock pin = \"clk32\") is 4.936 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.681 ns + Longest pin register " "Info: + Longest pin to register delay is 7.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rxd 1 PIN PIN_94 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_94; Fanout = 3; PIN Node = 'rxd'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rxd } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.605 ns) + CELL(0.607 ns) 7.681 ns rx:rx1\|read_en 2 REG LC_X18_Y8_N2 2 " "Info: 2: + IC(5.605 ns) + CELL(0.607 ns) = 7.681 ns; Loc. = LC_X18_Y8_N2; Fanout = 2; REG Node = 'rx:rx1\|read_en'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.212 ns" { rxd rx:rx1|read_en } "NODE_NAME" } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.076 ns ( 27.03 % ) " "Info: Total cell delay = 2.076 ns ( 27.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.605 ns ( 72.97 % ) " "Info: Total interconnect delay = 5.605 ns ( 72.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.681 ns" { rxd rx:rx1|read_en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.681 ns" { rxd rxd~out0 rx:rx1|read_en } { 0.000ns 0.000ns 5.605ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk32 destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"clk32\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk32 1 CLK PIN_16 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 82; CLK Node = 'clk32'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk32 } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns rx:rx1\|read_en 2 REG LC_X18_Y8_N2 2 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X18_Y8_N2; Fanout = 2; REG Node = 'rx:rx1\|read_en'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk32 rx:rx1|read_en } "NODE_NAME" } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk32 rx:rx1|read_en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk32 clk32~out0 rx:rx1|read_en } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.681 ns" { rxd rx:rx1|read_en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.681 ns" { rxd rxd~out0 rx:rx1|read_en } { 0.000ns 0.000ns 5.605ns } { 0.000ns 1.469ns 0.607ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk32 rx:rx1|read_en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk32 clk32~out0 rx:rx1|read_en } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk32 txd tx:tx1\|txd 7.609 ns register " "Info: tco from clock \"clk32\" to destination pin \"txd\" through register \"tx:tx1\|txd\" is 7.609 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk32 source 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk32\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk32 1 CLK PIN_16 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 82; CLK Node = 'clk32'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk32 } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns tx:tx1\|txd 2 REG LC_X17_Y10_N3 2 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X17_Y10_N3; Fanout = 2; REG Node = 'tx:tx1\|txd'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk32 tx:tx1|txd } "NODE_NAME" } } { "tx.vhd" "" { Text "F:/FPGA/feng_rs0/tx.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk32 tx:tx1|txd } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk32 clk32~out0 tx:tx1|txd } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "tx.vhd" "" { Text "F:/FPGA/feng_rs0/tx.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.603 ns + Longest register pin " "Info: + Longest register to pin delay is 4.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tx:tx1\|txd 1 REG LC_X17_Y10_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y10_N3; Fanout = 2; REG Node = 'tx:tx1\|txd'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { tx:tx1|txd } "NODE_NAME" } } { "tx.vhd" "" { Text "F:/FPGA/feng_rs0/tx.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.479 ns) + CELL(2.124 ns) 4.603 ns txd 2 PIN PIN_97 0 " "Info: 2: + IC(2.479 ns) + CELL(2.124 ns) = 4.603 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'txd'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.603 ns" { tx:tx1|txd txd } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 46.14 % ) " "Info: Total cell delay = 2.124 ns ( 46.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.479 ns ( 53.86 % ) " "Info: Total interconnect delay = 2.479 ns ( 53.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.603 ns" { tx:tx1|txd txd } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.603 ns" { tx:tx1|txd txd } { 0.000ns 2.479ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk32 tx:tx1|txd } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk32 clk32~out0 tx:tx1|txd } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.603 ns" { tx:tx1|txd txd } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.603 ns" { tx:tx1|txd txd } { 0.000ns 2.479ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}