{ "Info" "ITDB_TH_RESULT" "rx:rx1\|data_reg\[9\] rxd clk32 -4.575 ns register " "Info: th for register \"rx:rx1\|data_reg\[9\]\" (data pin = \"rxd\", clock pin = \"clk32\") is -4.575 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk32 destination 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk32\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk32 1 CLK PIN_16 82 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 82; CLK Node = 'clk32'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk32 } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns rx:rx1\|data_reg\[9\] 2 REG LC_X17_Y8_N5 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X17_Y8_N5; Fanout = 1; REG Node = 'rx:rx1\|data_reg\[9\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk32 rx:rx1|data_reg[9] } "NODE_NAME" } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk32 rx:rx1|data_reg[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk32 clk32~out0 rx:rx1|data_reg[9] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.372 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rxd 1 PIN PIN_94 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_94; Fanout = 3; PIN Node = 'rxd'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rxd } "NODE_NAME" } } { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.594 ns) + CELL(0.309 ns) 7.372 ns rx:rx1\|data_reg\[9\] 2 REG LC_X17_Y8_N5 1 " "Info: 2: + IC(5.594 ns) + CELL(0.309 ns) = 7.372 ns; Loc. = LC_X17_Y8_N5; Fanout = 1; REG Node = 'rx:rx1\|data_reg\[9\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.903 ns" { rxd rx:rx1|data_reg[9] } "NODE_NAME" } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 24.12 % ) " "Info: Total cell delay = 1.778 ns ( 24.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.594 ns ( 75.88 % ) " "Info: Total interconnect delay = 5.594 ns ( 75.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.372 ns" { rxd rx:rx1|data_reg[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.372 ns" { rxd rxd~out0 rx:rx1|data_reg[9] } { 0.000ns 0.000ns 5.594ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk32 rx:rx1|data_reg[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk32 clk32~out0 rx:rx1|data_reg[9] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.372 ns" { rxd rx:rx1|data_reg[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.372 ns" { rxd rxd~out0 rx:rx1|data_reg[9] } { 0.000ns 0.000ns 5.594ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 05 15:45:58 2009 " "Info: Processing ended: Thu Mar 05 15:45:58 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}