{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 05 15:45:44 2009 " "Info: Processing started: Thu Mar 05 15:45:44 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off serial -c serial " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serial -c serial" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ram1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram1-SYN " "Info: Found design unit 1: ram1-SYN" {  } { { "ram1.vhd" "" { Text "F:/FPGA/feng_rs0/ram1.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ram1 " "Info: Found entity 1: ram1" {  } { { "ram1.vhd" "" { Text "F:/FPGA/feng_rs0/ram1.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tx.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tx-behav2 " "Info: Found design unit 1: tx-behav2" {  } { { "tx.vhd" "" { Text "F:/FPGA/feng_rs0/tx.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tx " "Info: Found entity 1: tx" {  } { { "tx.vhd" "" { Text "F:/FPGA/feng_rs0/tx.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rx.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx-behav1 " "Info: Found design unit 1: rx-behav1" {  } { { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rx " "Info: Found entity 1: rx" {  } { { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenpin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fenpin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin-behav0 " "Info: Found design unit 1: fenpin-behav0" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serial.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file serial.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 serial-behav " "Info: Found design unit 1: serial-behav" {  } { { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 serial " "Info: Found entity 1: serial" {  } { { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "serial " "Info: Elaborating entity \"serial\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin fenpin:fp " "Info: Elaborating entity \"fenpin\" for hierarchy \"fenpin:fp\"" {  } { { "serial.vhd" "fp" { Text "F:/FPGA/feng_rs0/serial.vhd" 53 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx rx:rx1 " "Info: Elaborating entity \"rx\" for hierarchy \"rx:rx1\"" {  } { { "serial.vhd" "rx1" { Text "F:/FPGA/feng_rs0/serial.vhd" 54 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx tx:tx1 " "Info: Elaborating entity \"tx\" for hierarchy \"tx:tx1\"" {  } { { "serial.vhd" "tx1" { Text "F:/FPGA/feng_rs0/serial.vhd" 56 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram1 ram1:ram " "Info: Elaborating entity \"ram1\" for hierarchy \"ram1:ram\"" {  } { { "serial.vhd" "ram" { Text "F:/FPGA/feng_rs0/serial.vhd" 57 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram1:ram\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"ram1:ram\|altsyncram:altsyncram_component\"" {  } { { "ram1.vhd" "altsyncram_component" { Text "F:/FPGA/feng_rs0/ram1.vhd" 94 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}