{ "Info" "ISGN_ELABORATION_HEADER" "ram1:ram\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"ram1:ram\|altsyncram:altsyncram_component\"" {  } { { "ram1.vhd" "" { Text "F:/FPGA/feng_rs0/ram1.vhd" 94 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_06h1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_06h1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_06h1 " "Info: Found entity 1: altsyncram_06h1" {  } { { "db/altsyncram_06h1.tdf" "" { Text "F:/FPGA/feng_rs0/db/altsyncram_06h1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_06h1 ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated " "Info: Elaborating entity \"altsyncram_06h1\" for hierarchy \"ram1:ram\|altsyncram:altsyncram_component\|altsyncram_06h1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "wenlock ram_rclk " "Info: Duplicate register \"wenlock\" merged to single register \"ram_rclk\"" {  } { { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ren ram_wclk " "Info: Duplicate register \"ren\" merged to single register \"ram_wclk\"" {  } { { "serial.vhd" "" { Text "F:/FPGA/feng_rs0/serial.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|serial\|fenpin:fp\|state2 5 " "Info: State machine \"\|serial\|fenpin:fp\|state2\" contains 5 states" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 17 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|serial\|fenpin:fp\|state1 5 " "Info: State machine \"\|serial\|fenpin:fp\|state1\" contains 5 states" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 16 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|serial\|fenpin:fp\|state2 " "Info: Selected Auto state machine encoding method for state machine \"\|serial\|fenpin:fp\|state2\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 17 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|serial\|fenpin:fp\|state2 " "Info: Encoding result for state machine \"\|serial\|fenpin:fp\|state2\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "fenpin:fp\|state2.txd_start " "Info: Encoded state bit \"fenpin:fp\|state2.txd_start\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "fenpin:fp\|state2.rxd_sample " "Info: Encoded state bit \"fenpin:fp\|state2.rxd_sample\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "fenpin:fp\|state2.rxd_start " "Info: Encoded state bit \"fenpin:fp\|state2.rxd_start\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "fenpin:fp\|state2.txd_wait " "Info: Encoded state bit \"fenpin:fp\|state2.txd_wait\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "fenpin:fp\|state2.rxd_wait " "Info: Encoded state bit \"fenpin:fp\|state2.rxd_wait\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serial\|fenpin:fp\|state2.rxd_wait 00000 " "Info: State \"\|serial\|fenpin:fp\|state2.rxd_wait\" uses code string \"00000\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serial\|fenpin:fp\|state2.txd_wait 00011 " "Info: State \"\|serial\|fenpin:fp\|state2.txd_wait\" uses code string \"00011\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serial\|fenpin:fp\|state2.rxd_start 00101 " "Info: State \"\|serial\|fenpin:fp\|state2.rxd_start\" uses code string \"00101\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serial\|fenpin:fp\|state2.rxd_sample 01001 " "Info: State \"\|serial\|fenpin:fp\|state2.rxd_sample\" uses code string \"01001\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serial\|fenpin:fp\|state2.txd_start 10001 " "Info: State \"\|serial\|fenpin:fp\|state2.txd_start\" uses code string \"10001\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 17 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|serial\|fenpin:fp\|state1 " "Info: Selected Auto state machine encoding method for state machine \"\|serial\|fenpin:fp\|state1\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 16 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|serial\|fenpin:fp\|state1 " "Info: Encoding result for state machine \"\|serial\|fenpin:fp\|state1\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "fenpin:fp\|state1.rxd_wait " "Info: Encoded state bit \"fenpin:fp\|state1.rxd_wait\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "fenpin:fp\|state1.rxd_sample " "Info: Encoded state bit \"fenpin:fp\|state1.rxd_sample\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "fenpin:fp\|state1.rxd_start " "Info: Encoded state bit \"fenpin:fp\|state1.rxd_start\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "fenpin:fp\|state1.txd_start " "Info: Encoded state bit \"fenpin:fp\|state1.txd_start\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "fenpin:fp\|state1.txd_wait " "Info: Encoded state bit \"fenpin:fp\|state1.txd_wait\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serial\|fenpin:fp\|state1.txd_wait 00000 " "Info: State \"\|serial\|fenpin:fp\|state1.txd_wait\" uses code string \"00000\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serial\|fenpin:fp\|state1.txd_start 00011 " "Info: State \"\|serial\|fenpin:fp\|state1.txd_start\" uses code string \"00011\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serial\|fenpin:fp\|state1.rxd_start 00101 " "Info: State \"\|serial\|fenpin:fp\|state1.rxd_start\" uses code string \"00101\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serial\|fenpin:fp\|state1.rxd_sample 01001 " "Info: State \"\|serial\|fenpin:fp\|state1.rxd_sample\" uses code string \"01001\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serial\|fenpin:fp\|state1.rxd_wait 10001 " "Info: State \"\|serial\|fenpin:fp\|state1.rxd_wait\" uses code string \"10001\"" {  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "fenpin.vhd" "" { Text "F:/FPGA/feng_rs0/fenpin.vhd" 16 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "tx.vhd" "" { Text "F:/FPGA/feng_rs0/tx.vhd" 10 -1 0 } } { "tx.vhd" "" { Text "F:/FPGA/feng_rs0/tx.vhd" 16 -1 0 } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 16 -1 0 } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } } { "rx.vhd" "" { Text "F:/FPGA/feng_rs0/rx.vhd" 23 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "126 " "Info: Implemented 126 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "114 " "Info: Implemented 114 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 05 15:45:47 2009 " "Info: Processing ended: Thu Mar 05 15:45:47 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}