|serial
clk32 => tx:tx1.clk32
clk32 => rx:rx1.clk32
clk32 => fenpin:fp.clk32
clk32 => ram_rclk.CLK
clk32 => raddr[0].CLK
clk32 => raddr[1].CLK
clk32 => raddr[2].CLK
clk32 => raddr[3].CLK
clk32 => raddr[4].CLK
clk32 => wenlock.CLK
clk32 => wen.CLK
clk32 => waddr[0].CLK
clk32 => waddr[1].CLK
clk32 => waddr[2].CLK
clk32 => waddr[3].CLK
clk32 => waddr[4].CLK
clk32 => ram_wclk.CLK
clk32 => renlock.CLK
clk32 => ren.CLK
rstn => tx:tx1.rstn
rstn => rx:rx1.rstn
rstn => fenpin:fp.rstn
rstn => ren.ACLR
rstn => renlock.ACLR
rstn => ram_wclk.ACLR
rstn => waddr[4].ACLR
rstn => waddr[3].ACLR
rstn => waddr[2].ACLR
rstn => waddr[1].ACLR
rstn => waddr[0].ACLR
rstn => ram_rclk.ACLR
rstn => raddr[0].ACLR
rstn => raddr[1].ACLR
rstn => raddr[2].ACLR
rstn => raddr[3].ACLR
rstn => raddr[4].ACLR
rstn => wenlock.ACLR
rstn => wen.ACLR
rxd => rx:rx1.rxd
txd <= tx:tx1.txd


|serial|fenpin:fp
clk32 => clk_write~reg0.CLK
clk32 => clk_read~reg0.CLK
clk32 => reg2[0].CLK
clk32 => reg2[1].CLK
clk32 => reg2[2].CLK
clk32 => reg2[3].CLK
clk32 => reg2[4].CLK
clk32 => reg2[5].CLK
clk32 => reg2[6].CLK
clk32 => reg2[7].CLK
clk32 => reg2[8].CLK
clk32 => reg2[9].CLK
clk32 => reg2[10].CLK
clk32 => reg2[11].CLK
clk32 => reg1[0].CLK
clk32 => reg1[1].CLK
clk32 => reg1[2].CLK
clk32 => reg1[3].CLK
clk32 => reg1[4].CLK
clk32 => reg1[5].CLK
clk32 => reg1[6].CLK
clk32 => reg1[7].CLK
clk32 => reg1[8].CLK
clk32 => reg1[9].CLK
clk32 => reg1[10].CLK
clk32 => reg1[11].CLK
clk32 => state2~2.IN1
clk32 => state1~0.IN1
rstn => clk_write~reg0.ACLR
rstn => clk_read~reg0.ACLR
rstn => reg2[0].ACLR
rstn => reg2[1].ACLR
rstn => reg2[2].ACLR
rstn => reg2[3].ACLR
rstn => reg2[4].ACLR
rstn => reg2[5].ACLR
rstn => reg2[6].ACLR
rstn => reg2[7].ACLR
rstn => reg2[8].ACLR
rstn => reg2[9].ACLR
rstn => reg2[10].ACLR
rstn => reg2[11].ACLR
rstn => reg1[0].ACLR
rstn => reg1[1].ACLR
rstn => reg1[2].ACLR
rstn => reg1[3].ACLR
rstn => reg1[4].ACLR
rstn => reg1[5].ACLR
rstn => reg1[6].ACLR
rstn => reg1[7].ACLR
rstn => reg1[8].ACLR
rstn => reg1[9].ACLR
rstn => reg1[10].ACLR
rstn => reg1[11].ACLR
rstn => state2~3.IN1
rstn => state1~1.IN1
read_en => Selector2.IN3
read_en => Selector4.IN2
write_en => Selector0.IN3
write_en => Selector1.IN1
read_end => Selector4.IN4
read_end => Selector3.IN1
write_end => Selector1.IN3
write_end => Selector0.IN1
clk_read <= clk_read~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk_write <= clk_write~reg0.DB_MAX_OUTPUT_PORT_TYPE


|serial|rx:rx1
clk32 => data_reg[0].CLK
clk32 => data_reg[1].CLK
clk32 => data_reg[2].CLK
clk32 => data_reg[3].CLK
clk32 => data_reg[4].CLK
clk32 => data_reg[5].CLK
clk32 => data_reg[6].CLK
clk32 => data_reg[7].CLK
clk32 => data_reg[8].CLK
clk32 => data_reg[9].CLK
clk32 => rxd_data[0]~reg0.CLK
clk32 => rxd_data[1]~reg0.CLK
clk32 => rxd_data[2]~reg0.CLK
clk32 => rxd_data[3]~reg0.CLK
clk32 => rxd_data[4]~reg0.CLK
clk32 => rxd_data[5]~reg0.CLK
clk32 => rxd_data[6]~reg0.CLK
clk32 => rxd_data[7]~reg0.CLK
clk32 => state1.CLK
clk32 => r_end.CLK
clk32 => read_end~reg0.CLK
clk32 => read_en~reg0.CLK
rclk => data_reg~10.OUTPUTSELECT
rclk => data_reg~11.OUTPUTSELECT
rclk => data_reg~12.OUTPUTSELECT
rclk => data_reg~13.OUTPUTSELECT
rclk => data_reg~14.OUTPUTSELECT
rclk => data_reg~15.OUTPUTSELECT
rclk => data_reg~16.OUTPUTSELECT
rclk => data_reg~17.OUTPUTSELECT
rclk => data_reg~18.OUTPUTSELECT
rclk => data_reg~19.OUTPUTSELECT
rclk => r_end~1.OUTPUTSELECT
rclk => state1~0.OUTPUTSELECT
rstn => data_reg[0].PRESET
rstn => data_reg[1].PRESET
rstn => data_reg[2].PRESET
rstn => data_reg[3].PRESET
rstn => data_reg[4].PRESET
rstn => data_reg[5].PRESET
rstn => data_reg[6].PRESET
rstn => data_reg[7].PRESET
rstn => data_reg[8].PRESET
rstn => data_reg[9].PRESET
rstn => rxd_data[0]~reg0.ACLR
rstn => rxd_data[1]~reg0.ACLR
rstn => rxd_data[2]~reg0.ACLR
rstn => rxd_data[3]~reg0.ACLR
rstn => rxd_data[4]~reg0.ACLR
rstn => rxd_data[5]~reg0.ACLR
rstn => rxd_data[6]~reg0.ACLR
rstn => rxd_data[7]~reg0.ACLR
rstn => state1.PRESET
rstn => r_end.ACLR
rstn => read_end~reg0.ACLR
rstn => read_en~reg0.ACLR
rxd => state1~1.DATAB
rxd => data_reg~10.DATAB
rxd => read_en~0.DATAB
rxd_data[0] <= rxd_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rxd_data[1] <= rxd_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rxd_data[2] <= rxd_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rxd_data[3] <= rxd_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rxd_data[4] <= rxd_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rxd_data[5] <= rxd_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rxd_data[6] <= rxd_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rxd_data[7] <= rxd_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
read_en <= read_en~reg0.DB_MAX_OUTPUT_PORT_TYPE
read_end <= read_end~reg0.DB_MAX_OUTPUT_PORT_TYPE


|serial|tx:tx1
clk32 => data_reg[0].CLK
clk32 => data_reg[1].CLK
clk32 => data_reg[2].CLK
clk32 => data_reg[3].CLK
clk32 => data_reg[4].CLK
clk32 => data_reg[5].CLK
clk32 => data_reg[6].CLK
clk32 => data_reg[7].CLK
clk32 => data_reg[8].CLK
clk32 => data_reg[9].CLK
clk32 => data_reg[10].CLK
clk32 => state1.CLK
clk32 => write_end~reg0.CLK
clk32 => write_en~reg0.CLK
clk32 => txd~reg0.CLK
wclk => data_reg~11.OUTPUTSELECT
wclk => data_reg~12.OUTPUTSELECT
wclk => data_reg~13.OUTPUTSELECT
wclk => data_reg~14.OUTPUTSELECT
wclk => data_reg~15.OUTPUTSELECT
wclk => data_reg~16.OUTPUTSELECT
wclk => data_reg~17.OUTPUTSELECT
wclk => data_reg~18.OUTPUTSELECT
wclk => data_reg~19.OUTPUTSELECT
wclk => data_reg~20.OUTPUTSELECT
wclk => data_reg~21.OUTPUTSELECT
wclk => write_end~1.OUTPUTSELECT
wclk => state1~0.OUTPUTSELECT
rstn => data_reg[0].ACLR
rstn => data_reg[1].ACLR
rstn => data_reg[2].ACLR
rstn => data_reg[3].ACLR
rstn => data_reg[4].ACLR
rstn => data_reg[5].ACLR
rstn => data_reg[6].ACLR
rstn => data_reg[7].ACLR
rstn => data_reg[8].ACLR
rstn => data_reg[9].ACLR
rstn => data_reg[10].ACLR
rstn => state1.PRESET
rstn => write_end~reg0.ACLR
rstn => write_en~reg0.ACLR
rstn => txd~reg0.PRESET
wen => write_en~0.DATAB
wen => data_reg~0.OUTPUTSELECT
wen => data_reg~1.OUTPUTSELECT
wen => data_reg~2.OUTPUTSELECT
wen => data_reg~3.OUTPUTSELECT
wen => data_reg~4.OUTPUTSELECT
wen => data_reg~5.OUTPUTSELECT
wen => data_reg~6.OUTPUTSELECT
wen => data_reg~7.OUTPUTSELECT
wen => data_reg~8.OUTPUTSELECT
wen => data_reg~9.OUTPUTSELECT
wen => data_reg~10.OUTPUTSELECT
wen => state1~1.DATAB
txd_data[0] => data_reg~9.DATAB
txd_data[1] => data_reg~8.DATAB
txd_data[2] => data_reg~7.DATAB
txd_data[3] => data_reg~6.DATAB
txd_data[4] => data_reg~5.DATAB
txd_data[5] => data_reg~4.DATAB
txd_data[6] => data_reg~3.DATAB
txd_data[7] => data_reg~2.DATAB
write_en <= write_en~reg0.DB_MAX_OUTPUT_PORT_TYPE
write_end <= write_end~reg0.DB_MAX_OUTPUT_PORT_TYPE
txd <= txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|serial|ram1:ram
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]
rdaddress[1] => altsyncram:altsyncram_component.address_b[1]
rdaddress[2] => altsyncram:altsyncram_component.address_b[2]
rdaddress[3] => altsyncram:altsyncram_component.address_b[3]
rdaddress[4] => altsyncram:altsyncram_component.address_b[4]
rdclock => altsyncram:altsyncram_component.clock1
wraddress[0] => altsyncram:altsyncram_component.address_a[0]
wraddress[1] => altsyncram:altsyncram_component.address_a[1]
wraddress[2] => altsyncram:altsyncram_component.address_a[2]
wraddress[3] => altsyncram:altsyncram_component.address_a[3]
wraddress[4] => altsyncram:altsyncram_component.address_a[4]
wrclock => altsyncram:altsyncram_component.clock0
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_b[0]
q[1] <= altsyncram:altsyncram_component.q_b[1]
q[2] <= altsyncram:altsyncram_component.q_b[2]
q[3] <= altsyncram:altsyncram_component.q_b[3]
q[4] <= altsyncram:altsyncram_component.q_b[4]
q[5] <= altsyncram:altsyncram_component.q_b[5]
q[6] <= altsyncram:altsyncram_component.q_b[6]
q[7] <= altsyncram:altsyncram_component.q_b[7]


|serial|ram1:ram|altsyncram:altsyncram_component
wren_a => altsyncram_06h1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_06h1:auto_generated.data_a[0]
data_a[1] => altsyncram_06h1:auto_generated.data_a[1]
data_a[2] => altsyncram_06h1:auto_generated.data_a[2]
data_a[3] => altsyncram_06h1:auto_generated.data_a[3]
data_a[4] => altsyncram_06h1:auto_generated.data_a[4]
data_a[5] => altsyncram_06h1:auto_generated.data_a[5]
data_a[6] => altsyncram_06h1:auto_generated.data_a[6]
data_a[7] => altsyncram_06h1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_06h1:auto_generated.address_a[0]
address_a[1] => altsyncram_06h1:auto_generated.address_a[1]
address_a[2] => altsyncram_06h1:auto_generated.address_a[2]
address_a[3] => altsyncram_06h1:auto_generated.address_a[3]
address_a[4] => altsyncram_06h1:auto_generated.address_a[4]
address_b[0] => altsyncram_06h1:auto_generated.address_b[0]
address_b[1] => altsyncram_06h1:auto_generated.address_b[1]
address_b[2] => altsyncram_06h1:auto_generated.address_b[2]
address_b[3] => altsyncram_06h1:auto_generated.address_b[3]
address_b[4] => altsyncram_06h1:auto_generated.address_b[4]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_06h1:auto_generated.clock0
clock1 => altsyncram_06h1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_06h1:auto_generated.q_b[0]
q_b[1] <= altsyncram_06h1:auto_generated.q_b[1]
q_b[2] <= altsyncram_06h1:auto_generated.q_b[2]
q_b[3] <= altsyncram_06h1:auto_generated.q_b[3]
q_b[4] <= altsyncram_06h1:auto_generated.q_b[4]
q_b[5] <= altsyncram_06h1:auto_generated.q_b[5]
q_b[6] <= altsyncram_06h1:auto_generated.q_b[6]
q_b[7] <= altsyncram_06h1:auto_generated.q_b[7]


|serial|ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.ENA0