?? dds.tan.rpt
字號(hào):
; N/A ; 290.87 MHz ( period = 3.438 ns ) ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a0~porta_address_reg7 ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 2.875 ns ;
; N/A ; 290.87 MHz ( period = 3.438 ns ) ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a0~porta_address_reg8 ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 2.875 ns ;
; N/A ; 290.87 MHz ( period = 3.438 ns ) ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a0~porta_address_reg9 ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 2.875 ns ;
; N/A ; 395.57 MHz ( period = 2.528 ns ) ; REG10B:u3|DOUT[4] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a1~porta_address_reg4 ; CLK ; CLK ; None ; None ; 2.212 ns ;
; N/A ; 396.04 MHz ( period = 2.525 ns ) ; REG10B:u3|DOUT[4] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a0~porta_address_reg4 ; CLK ; CLK ; None ; None ; 2.212 ns ;
; N/A ; 414.59 MHz ( period = 2.412 ns ) ; REG10B:u3|DOUT[6] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a0~porta_address_reg6 ; CLK ; CLK ; None ; None ; 2.098 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[3] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg3 ; CLK ; CLK ; None ; None ; 1.966 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[7] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg7 ; CLK ; CLK ; None ; None ; 1.781 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[3] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a0~porta_address_reg3 ; CLK ; CLK ; None ; None ; 1.783 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[4] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg4 ; CLK ; CLK ; None ; None ; 1.769 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[7] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a1~porta_address_reg7 ; CLK ; CLK ; None ; None ; 1.744 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[9] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a0~porta_address_reg9 ; CLK ; CLK ; None ; None ; 1.695 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[6] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg6 ; CLK ; CLK ; None ; None ; 1.684 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[2] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg2 ; CLK ; CLK ; None ; None ; 1.661 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[1] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a0~porta_address_reg1 ; CLK ; CLK ; None ; None ; 1.669 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[0] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 ; CLK ; CLK ; None ; None ; 1.547 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[2] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a1~porta_address_reg2 ; CLK ; CLK ; None ; None ; 1.651 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[9] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a1~porta_address_reg9 ; CLK ; CLK ; None ; None ; 1.651 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[8] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a0~porta_address_reg8 ; CLK ; CLK ; None ; None ; 1.646 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[8] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg8 ; CLK ; CLK ; None ; None ; 1.635 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[0] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a1~porta_address_reg0 ; CLK ; CLK ; None ; None ; 1.531 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[1] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg1 ; CLK ; CLK ; None ; None ; 1.623 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[0] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a0~porta_address_reg0 ; CLK ; CLK ; None ; None ; 1.519 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[2] ; REG10B:u2|DOUT[9] ; CLK ; CLK ; None ; None ; 1.612 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[2] ; REG10B:u2|DOUT[8] ; CLK ; CLK ; None ; None ; 1.612 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[2] ; REG10B:u2|DOUT[7] ; CLK ; CLK ; None ; None ; 1.612 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[2] ; REG10B:u2|DOUT[6] ; CLK ; CLK ; None ; None ; 1.612 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[2] ; REG10B:u2|DOUT[5] ; CLK ; CLK ; None ; None ; 1.612 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[0] ; REG10B:u2|DOUT[9] ; CLK ; CLK ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[0] ; REG10B:u2|DOUT[8] ; CLK ; CLK ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[0] ; REG10B:u2|DOUT[7] ; CLK ; CLK ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[0] ; REG10B:u2|DOUT[6] ; CLK ; CLK ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[0] ; REG10B:u2|DOUT[5] ; CLK ; CLK ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[3] ; REG10B:u2|DOUT[9] ; CLK ; CLK ; None ; None ; 1.547 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[3] ; REG10B:u2|DOUT[8] ; CLK ; CLK ; None ; None ; 1.547 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[3] ; REG10B:u2|DOUT[7] ; CLK ; CLK ; None ; None ; 1.547 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[3] ; REG10B:u2|DOUT[6] ; CLK ; CLK ; None ; None ; 1.547 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[3] ; REG10B:u2|DOUT[5] ; CLK ; CLK ; None ; None ; 1.547 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[1] ; REG10B:u2|DOUT[9] ; CLK ; CLK ; None ; None ; 1.546 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[1] ; REG10B:u2|DOUT[8] ; CLK ; CLK ; None ; None ; 1.546 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[1] ; REG10B:u2|DOUT[7] ; CLK ; CLK ; None ; None ; 1.546 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[1] ; REG10B:u2|DOUT[6] ; CLK ; CLK ; None ; None ; 1.546 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[1] ; REG10B:u2|DOUT[5] ; CLK ; CLK ; None ; None ; 1.546 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[5] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg5 ; CLK ; CLK ; None ; None ; 1.355 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[4] ; REG10B:u2|DOUT[9] ; CLK ; CLK ; None ; None ; 1.506 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[4] ; REG10B:u2|DOUT[8] ; CLK ; CLK ; None ; None ; 1.506 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[4] ; REG10B:u2|DOUT[7] ?? 快捷鍵說明
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