LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS                                     -- 頂層設計
    PORT (  CLK : IN  STD_LOGIC;
          FWORD : IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
          FOUT  : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
             );
 END;
ARCHITECTURE one OF DDS_VHDL IS
     COMPONENT REG10B
        PORT (  LOAD :  IN STD_LOGIC;
                 DIN :  IN STD_LOGIC_VECTOR(9 DOWNTO 0);
                DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) );
    END COMPONENT;
 
    COMPONENT ADDER10B
       PORT (  A : IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
               B : IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
               S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)     );
    END COMPONENT;
    COMPONENT lpm_rom0
      PORT	( address	: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
		        clock	: IN STD_LOGIC ;
	            	q	: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)	);
    END COMPONENT; 
     SIGNAL F10B  : STD_LOGIC_VECTOR( 9 DOWNTO 0);
     SIGNAL A10B   : STD_LOGIC_VECTOR( 9 DOWNTO 0);
     SIGNAL B10B : STD_LOGIC_VECTOR( 9 DOWNTO 0);
    SIGNAL C10B : STD_LOGIC_VECTOR( 9 DOWNTO 0);
 BEGIN 
   F10B<=FWORD;
 
 u1 : ADDER10B  PORT MAP( A=>F10B,B=>B10B, S=>A10B );

 u2 :   REG10B  PORT MAP( DOUT=>B10B,DIN=>A10B, LOAD=>CLK );
u3 :   REG10B  PORT MAP( DOUT=>C10B,DIN=>B10B, LOAD=>CLK );
 u6 :  lpm_ROM0  PORT MAP( address=>C10B, q=>FOUT, clock=>CLK );
END;