-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--F1_q_a[0] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[0]_PORT_A_address_reg = DFFE(F1_q_a[0]_PORT_A_address, F1_q_a[0]_clock_0, , , );
F1_q_a[0]_clock_0 = CLK;
F1_q_a[0]_PORT_A_data_out = MEMORY(, , F1_q_a[0]_PORT_A_address_reg, , , , , , F1_q_a[0]_clock_0, , , , , );
F1_q_a[0]_PORT_A_data_out_reg = DFFE(F1_q_a[0]_PORT_A_data_out, F1_q_a[0]_clock_0, , , );
F1_q_a[0] = F1_q_a[0]_PORT_A_data_out_reg[0];


--F1_q_a[1] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[1]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[1]_PORT_A_address_reg = DFFE(F1_q_a[1]_PORT_A_address, F1_q_a[1]_clock_0, , , );
F1_q_a[1]_clock_0 = CLK;
F1_q_a[1]_PORT_A_data_out = MEMORY(, , F1_q_a[1]_PORT_A_address_reg, , , , , , F1_q_a[1]_clock_0, , , , , );
F1_q_a[1]_PORT_A_data_out_reg = DFFE(F1_q_a[1]_PORT_A_data_out, F1_q_a[1]_clock_0, , , );
F1_q_a[1] = F1_q_a[1]_PORT_A_data_out_reg[0];


--F1_q_a[2] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[2]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[2]_PORT_A_address_reg = DFFE(F1_q_a[2]_PORT_A_address, F1_q_a[2]_clock_0, , , );
F1_q_a[2]_clock_0 = CLK;
F1_q_a[2]_PORT_A_data_out = MEMORY(, , F1_q_a[2]_PORT_A_address_reg, , , , , , F1_q_a[2]_clock_0, , , , , );
F1_q_a[2]_PORT_A_data_out_reg = DFFE(F1_q_a[2]_PORT_A_data_out, F1_q_a[2]_clock_0, , , );
F1_q_a[2] = F1_q_a[2]_PORT_A_data_out_reg[0];


--F1_q_a[3] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[3]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[3]_PORT_A_address_reg = DFFE(F1_q_a[3]_PORT_A_address, F1_q_a[3]_clock_0, , , );
F1_q_a[3]_clock_0 = CLK;
F1_q_a[3]_PORT_A_data_out = MEMORY(, , F1_q_a[3]_PORT_A_address_reg, , , , , , F1_q_a[3]_clock_0, , , , , );
F1_q_a[3]_PORT_A_data_out_reg = DFFE(F1_q_a[3]_PORT_A_data_out, F1_q_a[3]_clock_0, , , );
F1_q_a[3] = F1_q_a[3]_PORT_A_data_out_reg[0];


--F1_q_a[4] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[4]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[4]_PORT_A_address_reg = DFFE(F1_q_a[4]_PORT_A_address, F1_q_a[4]_clock_0, , , );
F1_q_a[4]_clock_0 = CLK;
F1_q_a[4]_PORT_A_data_out = MEMORY(, , F1_q_a[4]_PORT_A_address_reg, , , , , , F1_q_a[4]_clock_0, , , , , );
F1_q_a[4]_PORT_A_data_out_reg = DFFE(F1_q_a[4]_PORT_A_data_out, F1_q_a[4]_clock_0, , , );
F1_q_a[4] = F1_q_a[4]_PORT_A_data_out_reg[0];


--F1_q_a[5] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[5]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[5]_PORT_A_address_reg = DFFE(F1_q_a[5]_PORT_A_address, F1_q_a[5]_clock_0, , , );
F1_q_a[5]_clock_0 = CLK;
F1_q_a[5]_PORT_A_data_out = MEMORY(, , F1_q_a[5]_PORT_A_address_reg, , , , , , F1_q_a[5]_clock_0, , , , , );
F1_q_a[5]_PORT_A_data_out_reg = DFFE(F1_q_a[5]_PORT_A_data_out, F1_q_a[5]_clock_0, , , );
F1_q_a[5] = F1_q_a[5]_PORT_A_data_out_reg[0];


--F1_q_a[6] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[6]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[6]_PORT_A_address_reg = DFFE(F1_q_a[6]_PORT_A_address, F1_q_a[6]_clock_0, , , );
F1_q_a[6]_clock_0 = CLK;
F1_q_a[6]_PORT_A_data_out = MEMORY(, , F1_q_a[6]_PORT_A_address_reg, , , , , , F1_q_a[6]_clock_0, , , , , );
F1_q_a[6]_PORT_A_data_out_reg = DFFE(F1_q_a[6]_PORT_A_data_out, F1_q_a[6]_clock_0, , , );
F1_q_a[6] = F1_q_a[6]_PORT_A_data_out_reg[0];


--F1_q_a[7] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[7]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[7]_PORT_A_address_reg = DFFE(F1_q_a[7]_PORT_A_address, F1_q_a[7]_clock_0, , , );
F1_q_a[7]_clock_0 = CLK;
F1_q_a[7]_PORT_A_data_out = MEMORY(, , F1_q_a[7]_PORT_A_address_reg, , , , , , F1_q_a[7]_clock_0, , , , , );
F1_q_a[7]_PORT_A_data_out_reg = DFFE(F1_q_a[7]_PORT_A_data_out, F1_q_a[7]_clock_0, , , );
F1_q_a[7] = F1_q_a[7]_PORT_A_data_out_reg[0];


--F1_q_a[8] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[8]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[8]_PORT_A_address_reg = DFFE(F1_q_a[8]_PORT_A_address, F1_q_a[8]_clock_0, , , );
F1_q_a[8]_clock_0 = CLK;
F1_q_a[8]_PORT_A_data_out = MEMORY(, , F1_q_a[8]_PORT_A_address_reg, , , , , , F1_q_a[8]_clock_0, , , , , );
F1_q_a[8]_PORT_A_data_out_reg = DFFE(F1_q_a[8]_PORT_A_data_out, F1_q_a[8]_clock_0, , , );
F1_q_a[8] = F1_q_a[8]_PORT_A_data_out_reg[0];


--F1_q_a[9] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[9]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[9]_PORT_A_address_reg = DFFE(F1_q_a[9]_PORT_A_address, F1_q_a[9]_clock_0, , , );
F1_q_a[9]_clock_0 = CLK;
F1_q_a[9]_PORT_A_data_out = MEMORY(, , F1_q_a[9]_PORT_A_address_reg, , , , , , F1_q_a[9]_clock_0, , , , , );
F1_q_a[9]_PORT_A_data_out_reg = DFFE(F1_q_a[9]_PORT_A_data_out, F1_q_a[9]_clock_0, , , );
F1_q_a[9] = F1_q_a[9]_PORT_A_data_out_reg[0];


--C2_DOUT[0] is REG10B:u3|DOUT[0]
--operation mode is normal

C2_DOUT[0]_lut_out = C1_DOUT[0];
C2_DOUT[0] = DFFEAS(C2_DOUT[0]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[1] is REG10B:u3|DOUT[1]
--operation mode is normal

C2_DOUT[1]_lut_out = C1_DOUT[1];
C2_DOUT[1] = DFFEAS(C2_DOUT[1]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[2] is REG10B:u3|DOUT[2]
--operation mode is normal

C2_DOUT[2]_lut_out = C1_DOUT[2];
C2_DOUT[2] = DFFEAS(C2_DOUT[2]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[3] is REG10B:u3|DOUT[3]
--operation mode is normal

C2_DOUT[3]_lut_out = C1_DOUT[3];
C2_DOUT[3] = DFFEAS(C2_DOUT[3]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[4] is REG10B:u3|DOUT[4]
--operation mode is normal

C2_DOUT[4]_lut_out = C1_DOUT[4];
C2_DOUT[4] = DFFEAS(C2_DOUT[4]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[5] is REG10B:u3|DOUT[5]
--operation mode is normal

C2_DOUT[5]_lut_out = C1_DOUT[5];
C2_DOUT[5] = DFFEAS(C2_DOUT[5]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[6] is REG10B:u3|DOUT[6]
--operation mode is normal

C2_DOUT[6]_lut_out = C1_DOUT[6];
C2_DOUT[6] = DFFEAS(C2_DOUT[6]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[7] is REG10B:u3|DOUT[7]
--operation mode is normal

C2_DOUT[7]_lut_out = C1_DOUT[7];
C2_DOUT[7] = DFFEAS(C2_DOUT[7]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[8] is REG10B:u3|DOUT[8]
--operation mode is normal

C2_DOUT[8]_lut_out = C1_DOUT[8];
C2_DOUT[8] = DFFEAS(C2_DOUT[8]_lut_out, CLK, VCC, , , , , , );


--C2_DOUT[9] is REG10B:u3|DOUT[9]
--operation mode is normal

C2_DOUT[9]_lut_out = C1_DOUT[9];
C2_DOUT[9] = DFFEAS(C2_DOUT[9]_lut_out, CLK, VCC, , , , , , );


--C1_DOUT[0] is REG10B:u2|DOUT[0]
--operation mode is arithmetic

C1_DOUT[0]_lut_out = C1_DOUT[0] $ FWORD[0];
C1_DOUT[0] = DFFEAS(C1_DOUT[0]_lut_out, CLK, VCC, , , , , , );

--C1L3 is REG10B:u2|DOUT[0]~71
--operation mode is arithmetic

C1L3 = CARRY(C1_DOUT[0] & FWORD[0]);


--C1_DOUT[1] is REG10B:u2|DOUT[1]
--operation mode is arithmetic

C1_DOUT[1]_carry_eqn = C1L3;
C1_DOUT[1]_lut_out = C1_DOUT[1] $ FWORD[1] $ C1_DOUT[1]_carry_eqn;
C1_DOUT[1] = DFFEAS(C1_DOUT[1]_lut_out, CLK, VCC, , , , , , );