?? 2410slib.lst
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ARM Macro Assembler Page 1
1 00000000 ;=======================================================
==============
2 00000000 ; File Name : 2410slib.s
3 00000000 ; Function : S3C2410 (Assembly)
4 00000000 ; Program : Shin, On Pil (SOP)
5 00000000 ; Date : March 09, 2002
6 00000000 ; Version : 0.0
7 00000000 ; History
8 00000000 ; 0.0 : Programming start (February 26,2002) -> SOP
9 00000000 ;=======================================================
==============
10 00000000
11 00000000 ;Interrupt, FIQ/IRQ disable
12 00000000 000000C0
NOINT EQU 0xc0 ; 1100 0000
13 00000000
14 00000000 ;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
15 00000000 GBLL THUMBCODE
16 00000000 [ {CONFIG} = 16
20 00000000 FALSE
THUMBCODE
SETL {FALSE}
21 00000000 ]
22 00000000
23 00000000 MACRO
24 00000000 MOV_PC_LR
25 00000000 [ THUMBCODE
26 00000000 bx lr
27 00000000 |
28 00000000 mov pc,lr
29 00000000 ]
30 00000000 MEND
31 00000000
32 00000000 AREA |C$$code|, CODE, READONLY
33 00000000 ;save cpsr and disable int, r0 = address to save cpsr
34 00000000 EXPORT EnterCritical
35 00000000 EnterCritical
36 00000000 E10F1000 mrs r1, cpsr
37 00000004 E5801000 str r1, [r0]
38 00000008 E38110C0 orr r1, r1, #NOINT
39 0000000C E12FF001 msr cpsr_cxsf, r1
40 00000010 E1A0F00E MOV PC,LR
41 00000014 ;restore cpsr, r0 = address to restore cpsr
42 00000014 EXPORT ExitCritical
43 00000014 ExitCritical
44 00000014 E5901000 ldr r1, [r0]
45 00000018 E12FF001 msr cpsr_cxsf, r1
46 0000001C MOV_PC_LR
25 0000001C [ THUMBCODE
28 0000001C E1A0F00E mov pc,lr
29 00000020 ]
47 00000020 ;==============
48 00000020 ; CPSR I,F bit
49 00000020 ;==============
50 00000020 ;int SET_IF(void);
51 00000020 ;The return value is current CPSR.
52 00000020 EXPORT SET_IF
53 00000020 SET_IF
54 00000020 ;This function works only if the processor is in previli
ARM Macro Assembler Page 2
ged mode.
55 00000020 E10F0000 mrs r0,cpsr
56 00000024 E1A01000 mov r1,r0
57 00000028 E38110C0 orr r1,r1,#NOINT
58 0000002C E12FF001 msr cpsr_cxsf,r1
59 00000030 MOV_PC_LR
25 00000030 [ THUMBCODE
28 00000030 E1A0F00E mov pc,lr
29 00000034 ]
60 00000034
61 00000034 ;void WR_IF(int cpsrValue);
62 00000034 EXPORT WR_IF
63 00000034 WR_IF
64 00000034 ;This function works only if the processor is in previli
ged mode.
65 00000034 E12FF000 msr cpsr_cxsf,r0
66 00000038 MOV_PC_LR
25 00000038 [ THUMBCODE
28 00000038 E1A0F00E mov pc,lr
29 0000003C ]
67 0000003C
68 0000003C
69 0000003C ;void CLR_IF(void);
70 0000003C EXPORT CLR_IF
71 0000003C CLR_IF
72 0000003C ;This function works only if the processor is in previli
ged mode.
73 0000003C E10F0000 mrs r0,cpsr
74 00000040 E3C000C0 bic r0,r0,#NOINT
75 00000044 E12FF000 msr cpsr_cxsf,r0
76 00000048 MOV_PC_LR
25 00000048 [ THUMBCODE
28 00000048 E1A0F00E mov pc,lr
29 0000004C ]
77 0000004C
78 0000004C ;====================================
79 0000004C ; MMU Cache/TLB/etc on/off functions
80 0000004C ;====================================
81 0000004C 00001000
R1_I EQU (1<<12)
82 0000004C 00000004
R1_C EQU (1<<2)
83 0000004C 00000002
R1_A EQU (1<<1)
84 0000004C 00000001
R1_M EQU (1)
85 0000004C 80000000
R1_iA EQU (1<<31)
86 0000004C 40000000
R1_nF EQU (1<<30)
87 0000004C
88 0000004C ;void MMU_EnableICache(void)
89 0000004C EXPORT MMU_EnableICache
90 0000004C MMU_EnableICache
91 0000004C EE110F10 mrc p15,0,r0,c1,c0,0
92 00000050 E3800A01 orr r0,r0,#R1_I
93 00000054 EE010F10 mcr p15,0,r0,c1,c0,0
94 00000058 MOV_PC_LR
25 00000058 [ THUMBCODE
ARM Macro Assembler Page 3
28 00000058 E1A0F00E mov pc,lr
29 0000005C ]
95 0000005C
96 0000005C ;void MMU_DisableICache(void)
97 0000005C EXPORT MMU_DisableICache
98 0000005C MMU_DisableICache
99 0000005C EE110F10 mrc p15,0,r0,c1,c0,0
100 00000060 E3C00A01 bic r0,r0,#R1_I
101 00000064 EE010F10 mcr p15,0,r0,c1,c0,0
102 00000068 MOV_PC_LR
25 00000068 [ THUMBCODE
28 00000068 E1A0F00E mov pc,lr
29 0000006C ]
103 0000006C
104 0000006C ;void MMU_EnableDCache(void)
105 0000006C EXPORT MMU_EnableDCache
106 0000006C MMU_EnableDCache
107 0000006C EE110F10 mrc p15,0,r0,c1,c0,0
108 00000070 E3800004 orr r0,r0,#R1_C
109 00000074 EE010F10 mcr p15,0,r0,c1,c0,0
110 00000078 MOV_PC_LR
25 00000078 [ THUMBCODE
28 00000078 E1A0F00E mov pc,lr
29 0000007C ]
111 0000007C
112 0000007C ;void MMU_DisableDCache(void)
113 0000007C EXPORT MMU_DisableDCache
114 0000007C MMU_DisableDCache
115 0000007C EE110F10 mrc p15,0,r0,c1,c0,0
116 00000080 E3C00004 bic r0,r0,#R1_C
117 00000084 EE010F10 mcr p15,0,r0,c1,c0,0
118 00000088 MOV_PC_LR
25 00000088 [ THUMBCODE
28 00000088 E1A0F00E mov pc,lr
29 0000008C ]
119 0000008C
120 0000008C ;void MMU_EnableAlignFault(void)
121 0000008C EXPORT MMU_EnableAlignFault
122 0000008C MMU_EnableAlignFault
123 0000008C EE110F10 mrc p15,0,r0,c1,c0,0
124 00000090 E3800002 orr r0,r0,#R1_A
125 00000094 EE010F10 mcr p15,0,r0,c1,c0,0
126 00000098 MOV_PC_LR
25 00000098 [ THUMBCODE
28 00000098 E1A0F00E mov pc,lr
29 0000009C ]
127 0000009C
128 0000009C ;void MMU_DisableAlignFault(void)
129 0000009C EXPORT MMU_DisableAlignFault
130 0000009C MMU_DisableAlignFault
131 0000009C EE110F10 mrc p15,0,r0,c1,c0,0
132 000000A0 E3C00002 bic r0,r0,#R1_A
133 000000A4 EE010F10 mcr p15,0,r0,c1,c0,0
134 000000A8 MOV_PC_LR
25 000000A8 [ THUMBCODE
28 000000A8 E1A0F00E mov pc,lr
29 000000AC ]
135 000000AC
136 000000AC ;void MMU_EnableMMU(void)
ARM Macro Assembler Page 4
137 000000AC EXPORT MMU_EnableMMU
138 000000AC MMU_EnableMMU
139 000000AC EE110F10 mrc p15,0,r0,c1,c0,0
140 000000B0 E3800001 orr r0,r0,#R1_M
141 000000B4 EE010F10 mcr p15,0,r0,c1,c0,0
142 000000B8 MOV_PC_LR
25 000000B8 [ THUMBCODE
28 000000B8 E1A0F00E mov pc,lr
29 000000BC ]
143 000000BC
144 000000BC ;void MMU_DisableMMU(void)
145 000000BC EXPORT MMU_DisableMMU
146 000000BC MMU_DisableMMU
147 000000BC EE110F10 mrc p15,0,r0,c1,c0,0
148 000000C0 E3C00001 bic r0,r0,#R1_M
149 000000C4 EE010F10 mcr p15,0,r0,c1,c0,0
150 000000C8 MOV_PC_LR
25 000000C8 [ THUMBCODE
28 000000C8 E1A0F00E mov pc,lr
29 000000CC ]
151 000000CC
152 000000CC ;void MMU_SetFastBusMode(void)
153 000000CC ; FCLK:HCLK= 1:1
154 000000CC EXPORT MMU_SetFastBusMode
155 000000CC MMU_SetFastBusMode
156 000000CC EE110F10 mrc p15,0,r0,c1,c0,0
157 000000D0 E3C00103 bic r0,r0,#R1_iA:OR:R1_nF
158 000000D4 EE010F10 mcr p15,0,r0,c1,c0,0
159 000000D8 MOV_PC_LR
25 000000D8 [ THUMBCODE
28 000000D8 E1A0F00E mov pc,lr
29 000000DC ]
160 000000DC
161 000000DC ;void MMU_SetAsyncBusMode(void)
162 000000DC ; FCLK:HCLK= 1:2
163 000000DC EXPORT MMU_SetAsyncBusMode
164 000000DC MMU_SetAsyncBusMode
165 000000DC EE110F10 mrc p15,0,r0,c1,c0,0
166 000000E0 E3800103 orr r0,r0,#R1_nF:OR:R1_iA
167 000000E4 EE010F10 mcr p15,0,r0,c1,c0,0
168 000000E8 MOV_PC_LR
25 000000E8 [ THUMBCODE
28 000000E8 E1A0F00E mov pc,lr
29 000000EC ]
169 000000EC
170 000000EC ;=========================
171 000000EC ; Set TTBase
172 000000EC ;=========================
173 000000EC ;void MMU_SetTTBase(int base)
174 000000EC EXPORT MMU_SetTTBase
175 000000EC MMU_SetTTBase
176 000000EC ;ro=TTBase
177 000000EC EE020F10 mcr p15,0,r0,c2,c0,0
178 000000F0 MOV_PC_LR
25 000000F0 [ THUMBCODE
28 000000F0 E1A0F00E mov pc,lr
29 000000F4 ]
179 000000F4
180 000000F4 ;=========================
ARM Macro Assembler Page 5
181 000000F4 ; Set Domain
182 000000F4 ;=========================
183 000000F4 ;void MMU_SetDomain(int domain)
184 000000F4 EXPORT MMU_SetDomain
185 000000F4 MMU_SetDomain
186 000000F4 ;ro=domain
187 000000F4 EE030F10 mcr p15,0,r0,c3,c0,0
188 000000F8 E1A0F00E MOV PC,LR
189 000000FC
190 000000FC ;=========================
191 000000FC ; ICache/DCache functions
192 000000FC ;=========================
193 000000FC ;void MMU_InvalidateIDCache(void)
194 000000FC EXPORT MMU_InvalidateIDCache
195 000000FC MMU_InvalidateIDCache
196 000000FC EE070F17 mcr p15,0,r0,c7,c7,0
197 00000100 MOV_PC_LR
25 00000100 [ THUMBCODE
28 00000100 E1A0F00E mov pc,lr
29 00000104 ]
198 00000104
199 00000104 ;void MMU_InvalidateICache(void)
200 00000104 EXPORT MMU_InvalidateICache
201 00000104 MMU_InvalidateICache
202 00000104 EE070F15 mcr p15,0,r0,c7,c5,0
203 00000108 MOV_PC_LR
25 00000108 [ THUMBCODE
28 00000108 E1A0F00E mov pc,lr
29 0000010C ]
204 0000010C
205 0000010C ;void MMU_InvalidateICacheMVA(U32 mva)
206 0000010C EXPORT MMU_InvalidateICacheMVA
207 0000010C MMU_InvalidateICacheMVA
208 0000010C ;r0=mva
209 0000010C EE070F35 mcr p15,0,r0,c7,c5,1
210 00000110 MOV_PC_LR
25 00000110 [ THUMBCODE
28 00000110 E1A0F00E mov pc,lr
29 00000114 ]
211 00000114
212 00000114 ;void MMU_PrefetchICacheMVA(U32 mva)
213 00000114 EXPORT MMU_PrefetchICacheMVA
214 00000114 MMU_PrefetchICacheMVA
215 00000114 ;r0=mva
216 00000114 EE070F3D mcr p15,0,r0,c7,c13,1
217 00000118 MOV_PC_LR
25 00000118 [ THUMBCODE
28 00000118 E1A0F00E mov pc,lr
29 0000011C ]
218 0000011C
219 0000011C ;void MMU_InvalidateDCache(void)
220 0000011C EXPORT MMU_InvalidateDCache
221 0000011C MMU_InvalidateDCache
222 0000011C EE070F16 mcr p15,0,r0,c7,c6,0
223 00000120 MOV_PC_LR
25 00000120 [ THUMBCODE
28 00000120 E1A0F00E mov pc,lr
29 00000124 ]
224 00000124
ARM Macro Assembler Page 6
225 00000124 ;void MMU_InvalidateDCacheMVA(U32 mva)
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