226 00000124                 EXPORT           MMU_InvalidateDCacheMVA
  227 00000124         MMU_InvalidateDCacheMVA
  228 00000124         ;r0=mva
  229 00000124 EE070F36        mcr              p15,0,r0,c7,c6,1
  230 00000128                 MOV_PC_LR
   25 00000128                 [                THUMBCODE
   28 00000128 E1A0F00E        mov              pc,lr
   29 0000012C                 ]
  231 0000012C         
  232 0000012C         ;void MMU_CleanDCacheMVA(U32 mva)
  233 0000012C                 EXPORT           MMU_CleanDCacheMVA
  234 0000012C         MMU_CleanDCacheMVA
  235 0000012C         ;r0=mva
  236 0000012C EE070F3A        mcr              p15,0,r0,c7,c10,1
  237 00000130                 MOV_PC_LR
   25 00000130                 [                THUMBCODE
   28 00000130 E1A0F00E        mov              pc,lr
   29 00000134                 ]
  238 00000134         
  239 00000134         ;void MMU_CleanInvalidateDCacheMVA(U32 mva)
  240 00000134                 EXPORT           MMU_CleanInvalidateDCacheMVA
  241 00000134         MMU_CleanInvalidateDCacheMVA
  242 00000134         ;r0=mva
  243 00000134 EE070F3E        mcr              p15,0,r0,c7,c14,1
  244 00000138                 MOV_PC_LR
   25 00000138                 [                THUMBCODE
   28 00000138 E1A0F00E        mov              pc,lr
   29 0000013C                 ]
  245 0000013C         
  246 0000013C         ;void MMU_CleanDCacheIndex(U32 index)
  247 0000013C                 EXPORT           MMU_CleanDCacheIndex
  248 0000013C         MMU_CleanDCacheIndex
  249 0000013C         ;r0=index 
  250 0000013C EE070F5A        mcr              p15,0,r0,c7,c10,2
  251 00000140                 MOV_PC_LR
   25 00000140                 [                THUMBCODE
   28 00000140 E1A0F00E        mov              pc,lr
   29 00000144                 ]
  252 00000144         
  253 00000144         ;void MMU_CleanInvalidateDCacheIndex(U32 index) 
  254 00000144                 EXPORT           MMU_CleanInvalidateDCacheIndex
  255 00000144         MMU_CleanInvalidateDCacheIndex
  256 00000144         ;r0=index
  257 00000144 EE070F5E        mcr              p15,0,r0,c7,c14,2
  258 00000148                 MOV_PC_LR
   25 00000148                 [                THUMBCODE
   28 00000148 E1A0F00E        mov              pc,lr
   29 0000014C                 ]
  259 0000014C         
  260 0000014C         ;void MMU_WaitForInterrupt(void)
  261 0000014C                 EXPORT           MMU_WaitForInterrupt
  262 0000014C         MMU_WaitForInterrupt
  263 0000014C EE070F90        mcr              p15,0,r0,c7,c0,4
  264 00000150                 MOV_PC_LR
   25 00000150                 [                THUMBCODE
   28 00000150 E1A0F00E        mov              pc,lr
   29 00000154                 ]
  265 00000154         



ARM Macro Assembler    Page 7 


  266 00000154         ;===============
  267 00000154         ; TLB functions
  268 00000154         ;===============
  269 00000154         ;voic MMU_InvalidateTLB(void)
  270 00000154                 EXPORT           MMU_InvalidateTLB
  271 00000154         MMU_InvalidateTLB
  272 00000154 EE080F17        mcr              p15,0,r0,c8,c7,0
  273 00000158                 MOV_PC_LR
   25 00000158                 [                THUMBCODE
   28 00000158 E1A0F00E        mov              pc,lr
   29 0000015C                 ]
  274 0000015C         
  275 0000015C         ;void MMU_InvalidateITLB(void)
  276 0000015C                 EXPORT           MMU_InvalidateITLB
  277 0000015C         MMU_InvalidateITLB
  278 0000015C EE080F15        mcr              p15,0,r0,c8,c5,0
  279 00000160                 MOV_PC_LR
   25 00000160                 [                THUMBCODE
   28 00000160 E1A0F00E        mov              pc,lr
   29 00000164                 ]
  280 00000164         
  281 00000164         ;void MMU_InvalidateITLBMVA(U32 mva)
  282 00000164                 EXPORT           MMU_InvalidateITLBMVA
  283 00000164         MMU_InvalidateITLBMVA
  284 00000164         ;ro=mva
  285 00000164 EE080F35        mcr              p15,0,r0,c8,c5,1
  286 00000168                 MOV_PC_LR
   25 00000168                 [                THUMBCODE
   28 00000168 E1A0F00E        mov              pc,lr
   29 0000016C                 ]
  287 0000016C         
  288 0000016C         ;void MMU_InvalidateDTLB(void)
  289 0000016C                 EXPORT           MMU_InvalidateDTLB
  290 0000016C         MMU_InvalidateDTLB
  291 0000016C EE080F16        mcr              p15,0,r0,c8,c6,0
  292 00000170                 MOV_PC_LR
   25 00000170                 [                THUMBCODE
   28 00000170 E1A0F00E        mov              pc,lr
   29 00000174                 ]
  293 00000174         
  294 00000174         ;void MMU_InvalidateDTLBMVA(U32 mva)
  295 00000174                 EXPORT           MMU_InvalidateDTLBMVA
  296 00000174         MMU_InvalidateDTLBMVA
  297 00000174         ;r0=mva
  298 00000174 EE080F36        mcr              p15,0,r0,c8,c6,1
  299 00000178                 MOV_PC_LR
   25 00000178                 [                THUMBCODE
   28 00000178 E1A0F00E        mov              pc,lr
   29 0000017C                 ]
  300 0000017C         
  301 0000017C         ;=================
  302 0000017C         ; Cache lock down
  303 0000017C         ;=================
  304 0000017C         ;void MMU_SetDCacheLockdownBase(U32 base)
  305 0000017C                 EXPORT           MMU_SetDCacheLockdownBase
  306 0000017C         MMU_SetDCacheLockdownBase
  307 0000017C         ;r0= victim & lockdown base
  308 0000017C EE090F10        mcr              p15,0,r0,c9,c0,0
  309 00000180                 MOV_PC_LR



ARM Macro Assembler    Page 8 


   25 00000180                 [                THUMBCODE
   28 00000180 E1A0F00E        mov              pc,lr
   29 00000184                 ]
  310 00000184         
  311 00000184         ;void MMU_SetICacheLockdownBase(U32 base)
  312 00000184                 EXPORT           MMU_SetICacheLockdownBase
  313 00000184         MMU_SetICacheLockdownBase
  314 00000184         ;r0= victim & lockdown base
  315 00000184 EE090F30        mcr              p15,0,r0,c9,c0,1
  316 00000188                 MOV_PC_LR
   25 00000188                 [                THUMBCODE
   28 00000188 E1A0F00E        mov              pc,lr
   29 0000018C                 ]
  317 0000018C         
  318 0000018C         ;=================
  319 0000018C         ; TLB lock down
  320 0000018C         ;=================
  321 0000018C         ;void MMU_SetDTLBLockdown(U32 baseVictim)
  322 0000018C                 EXPORT           MMU_SetDTLBLockdown
  323 0000018C         MMU_SetDTLBLockdown
  324 0000018C         ;r0= baseVictim
  325 0000018C EE0A0F10        mcr              p15,0,r0,c10,c0,0
  326 00000190                 MOV_PC_LR
   25 00000190                 [                THUMBCODE
   28 00000190 E1A0F00E        mov              pc,lr
   29 00000194                 ]
  327 00000194         
  328 00000194         ;void MMU_SetITLBLockdown(U32 baseVictim)
  329 00000194                 EXPORT           MMU_SetITLBLockdown
  330 00000194         MMU_SetITLBLockdown
  331 00000194         ;r0= baseVictim
  332 00000194 EE0A0F30        mcr              p15,0,r0,c10,c0,1
  333 00000198                 MOV_PC_LR
   25 00000198                 [                THUMBCODE
   28 00000198 E1A0F00E        mov              pc,lr
   29 0000019C                 ]
  334 0000019C         
  335 0000019C         ;============
  336 0000019C         ; Process ID
  337 0000019C         ;============
  338 0000019C         ;void MMU_SetProcessId(U32 pid)
  339 0000019C                 EXPORT           MMU_SetProcessId
  340 0000019C         MMU_SetProcessId
  341 0000019C         ;r0= pid
  342 0000019C EE0D0F10        mcr              p15,0,r0,c13,c0,0
  343 000001A0                 MOV_PC_LR
   25 000001A0                 [                THUMBCODE
   28 000001A0 E1A0F00E        mov              pc,lr
   29 000001A4                 ]
  344 000001A4         
  345 000001A4                 END
Command Line: --debug --xref --device=DARMSS9 --apcs=interwork -o.\obj\2410slib
.o -I..\common\inc -IC:\Keil\ARM\INC\Samsung --list=.\lst\2410slib.lst 2410slib
.s



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

C$$code 00000000

Symbol: C$$code
   Definitions
      At line 32 in file 2410slib.s
   Uses
      None
Comment: C$$code unused
CLR_IF 0000003C

Symbol: CLR_IF
   Definitions
      At line 71 in file 2410slib.s
   Uses
      At line 70 in file 2410slib.s
Comment: CLR_IF used once
EnterCritical 00000000

Symbol: EnterCritical
   Definitions
      At line 35 in file 2410slib.s
   Uses
      At line 34 in file 2410slib.s
Comment: EnterCritical used once
ExitCritical 00000014

Symbol: ExitCritical
   Definitions
      At line 43 in file 2410slib.s
   Uses
      At line 42 in file 2410slib.s
Comment: ExitCritical used once
MMU_CleanDCacheIndex 0000013C

Symbol: MMU_CleanDCacheIndex
   Definitions
      At line 248 in file 2410slib.s
   Uses
      At line 247 in file 2410slib.s
Comment: MMU_CleanDCacheIndex used once
MMU_CleanDCacheMVA 0000012C

Symbol: MMU_CleanDCacheMVA
   Definitions
      At line 234 in file 2410slib.s
   Uses
      At line 233 in file 2410slib.s
Comment: MMU_CleanDCacheMVA used once
MMU_CleanInvalidateDCacheIndex 00000144

Symbol: MMU_CleanInvalidateDCacheIndex
   Definitions
      At line 255 in file 2410slib.s
   Uses
      At line 254 in file 2410slib.s
Comment: MMU_CleanInvalidateDCacheIndex used once
MMU_CleanInvalidateDCacheMVA 00000134

Symbol: MMU_CleanInvalidateDCacheMVA



ARM Macro Assembler    Page 2 Alphabetic symbol ordering
Relocatable symbols

   Definitions
      At line 241 in file 2410slib.s
   Uses
      At line 240 in file 2410slib.s
Comment: MMU_CleanInvalidateDCacheMVA used once
MMU_DisableAlignFault 0000009C

Symbol: MMU_DisableAlignFault
   Definitions
      At line 130 in file 2410slib.s
   Uses
      At line 129 in file 2410slib.s
Comment: MMU_DisableAlignFault used once
MMU_DisableDCache 0000007C

Symbol: MMU_DisableDCache
   Definitions
      At line 114 in file 2410slib.s
   Uses
      At line 113 in file 2410slib.s
Comment: MMU_DisableDCache used once
MMU_DisableICache 0000005C

Symbol: MMU_DisableICache
   Definitions
      At line 98 in file 2410slib.s
   Uses
      At line 97 in file 2410slib.s
Comment: MMU_DisableICache used once
MMU_DisableMMU 000000BC

Symbol: MMU_DisableMMU
   Definitions
      At line 146 in file 2410slib.s
   Uses
      At line 145 in file 2410slib.s
Comment: MMU_DisableMMU used once
MMU_EnableAlignFault 0000008C

Symbol: MMU_EnableAlignFault
   Definitions
      At line 122 in file 2410slib.s
   Uses
      At line 121 in file 2410slib.s
Comment: MMU_EnableAlignFault used once
MMU_EnableDCache 0000006C

Symbol: MMU_EnableDCache
   Definitions
      At line 106 in file 2410slib.s
   Uses
      At line 105 in file 2410slib.s
Comment: MMU_EnableDCache used once
MMU_EnableICache 0000004C

Symbol: MMU_EnableICache
   Definitions
      At line 90 in file 2410slib.s
   Uses



ARM Macro Assembler    Page 3 Alphabetic symbol ordering
Relocatable symbols

      At line 89 in file 2410slib.s
Comment: MMU_EnableICache used once
MMU_EnableMMU 000000AC

Symbol: MMU_EnableMMU
   Definitions
      At line 138 in file 2410slib.s
   Uses
      At line 137 in file 2410slib.s
Comment: MMU_EnableMMU used once
MMU_InvalidateDCache 0000011C

Symbol: MMU_InvalidateDCache