#   undef  INCLUDE_DEBUG_STORE		/* Debug Store (BTS/PEBS) */#   ifdef  INCLUDE_DEBUG_STORE#       define DS_SYS_MODE   FALSE	/* TRUE system mode, FALSE task mode */#       define BTS_ENABLED   TRUE	/* BTS TRUE enable, FALSE disable */#       define BTS_INT_MODE  TRUE	/* BTS TRUE int mode, FALSE circular */#       define BTS_BUF_MODE  TRUE	/* BTS TRUE buffer mode, FALSE bus */#       define PEBS_ENABLED  TRUE	/* PEBS TRUE enable, FALSE disable */#       define PEBS_EVENT    PEBS_REPLAY		/* PEBS event */#       define PEBS_METRIC   PEBS_2NDL_CACHE_LOAD_MISS	/* PEBS metric */#       define PEBS_OS       TRUE	/* PEBS TRUE supervisor, FALSE usr */#       define PEBS_RESET    -1LL	/* PEBS default reset counter value */#   endif /* INCLUDE_DEBUG_STORE */#endif	/* (CPU == PENTIUM4) */#endif	/* (CPU == I80386) || (CPU == I80486) */#define IO_ADRS_ELC	0x240#define INT_LVL_ELC	0x0b#define MEM_ADRS_ELC	0xc8000#define MEM_SIZE_ELC	0x4000#define CONFIG_ELC	0	/* 0=EEPROM 1=RJ45+AUI 2=RJ45+BNC */#define IO_ADRS_ULTRA	0x240#define INT_LVL_ULTRA	0x0b#define MEM_ADRS_ULTRA	0xc8000#define MEM_SIZE_ULTRA	0x4000#define CONFIG_ULTRA	0	/* 0=EEPROM 1=RJ45+AUI 2=RJ45+BNC */#define IO_ADRS_EEX	0x240#define INT_LVL_EEX	0x0b#define NTFDS_EEX	0x00#define CONFIG_EEX	0	/* 0=EEPROM  1=AUI  2=BNC  3=RJ45 */				/* Auto-detect is not supported, so choose */				/* the right one you're going to use */#define IO_ADRS_ELT	0x240#define INT_LVL_ELT	0x0b#define NRF_ELT		0x00#define CONFIG_ELT	0	/* 0=EEPROM 1=AUI  2=BNC  3=RJ45 */#define IO_ADRS_ENE	0x300#define INT_LVL_ENE	0x05				/* Hardware jumper is used to set */				/* RJ45(Twisted Pair) AUI(Thick) BNC(Thin) */#define IO_ADRS_ESMC	0x300#define INT_LVL_ESMC	0x0b#define CONFIG_ESMC	0	/* 0=EEPROM 1=AUI  2=BNC 3=RJ45 */#define RX_MODE_ESMC	0	/* 0=interrupt level 1=task level */#ifdef	INCLUDE_EEX32#   define INCLUDE_EI		/* include 82596 driver */#   define INT_LVL_EI	0x0b#   define EI_SYSBUS	0x44	/* 82596 SYSBUS value */#   define EI_POOL_ADRS	NONE	/* memory allocated from system memory */#endif	/* INCLUDE_EEX32 *//* * ATA_TYPE <ataTypes[][]> ATA_GEO_FORCE parameters  * * ATA_TYPE is defined in h/drv/hdisk/ataDrv.h.  The <ataTypes[][]> table * is declared in sysLib.c. *//* controller zero device zero */#define ATA_CTRL0_DRV0_CYL  (761)   /* ATA 0, device 0 cylinders */#define ATA_CTRL0_DRV0_HDS  (8)     /* ATA 0, device 0 heads */#define ATA_CTRL0_DRV0_SPT  (39)    /* ATA 0, device 0 sectors per track */#define ATA_CTRL0_DRV0_BPS  (512)   /* ATA 0, device 0 bytes per sector */#define ATA_CTRL0_DRV0_WPC  (0xff)  /* ATA 0, device 0 write pre-compensation *//* controller zero device one */#define ATA_CTRL0_DRV1_CYL  (761)   /* ATA 0, device 1 cylinders */#define ATA_CTRL0_DRV1_HDS  (8)     /* ATA 0, device 1 heads */#define ATA_CTRL0_DRV1_SPT  (39)    /* ATA 0, device 1 sectors per track */#define ATA_CTRL0_DRV1_BPS  (512)   /* ATA 0, device 1 bytes per sector */#define ATA_CTRL0_DRV1_WPC  (0xff)  /* ATA 0, device 1 write pre-compensation *//* controller one device zero */#define ATA_CTRL1_DRV0_CYL  (761)   /* ATA 1, device 0 cylinders */#define ATA_CTRL1_DRV0_HDS  (8)     /* ATA 1, device 0 heads */#define ATA_CTRL1_DRV0_SPT  (39)    /* ATA 1, device 0 sectors per track */#define ATA_CTRL1_DRV0_BPS  (512)   /* ATA 1, device 0 bytes per sector */#define ATA_CTRL1_DRV0_WPC  (0xff)  /* ATA 1, device 0 write pre-compensation *//* controller one device one */#define ATA_CTRL1_DRV1_CYL  (761)   /* ATA 1, device 1 cylinders */#define ATA_CTRL1_DRV1_HDS  (8)     /* ATA 1, device 1 heads */#define ATA_CTRL1_DRV1_SPT  (39)    /* ATA 1, device 1 sectors per track */#define ATA_CTRL1_DRV1_BPS  (512)   /* ATA 1, device 1 bytes per sector */#define ATA_CTRL1_DRV1_WPC  (0xff)  /* ATA 1, device 1 write pre-compensation *//* * ATA_RESOURCE <ataResources[]> parameters  * * ATA_RESOURCES is defined in h/drv/pcmcia/pccardLib.h.  The <ataResources[]> * table is declared in sysLib.c.  Defaults are based on the pcPentium BSP. *//* ATA controller zero ataResources[] parameters */#define ATA0_VCC          (5)          /* ATA 0 Vcc (3 or 5 volts) */#define ATA0_VPP          (0)          /* ATA 0 Vpp (5 or 12 volts or 0) */#define ATA0_IO_START0    (0x1f0)      /* Start I/O Address 0 for ATA 0 */#define ATA0_IO_START1    (0x3f6)      /* Start I/O Address 1 for ATA 0 */#define ATA0_IO_STOP0     (0x1f7)      /* Stop I/O Address for ATA 0 */#define ATA0_IO_STOP1     (0x3f7)      /* Stop I/O Address for ATA 0 */#define ATA0_EXTRA_WAITS  (0)          /* ATA 0 extra wait states (0-2) */#define ATA0_MEM_START    (0)          /* ATA 0 memory start address */#define ATA0_MEM_STOP     (0)          /* ATA 0 memory start address */#define ATA0_MEM_WAITS    (0)          /* ATA 0 memory extra wait states */#define ATA0_MEM_OFFSET   (0)          /* ATA 0 memory offset */#define ATA0_MEM_LENGTH   (0)          /* ATA 0 memory offset */#define ATA0_CTRL_TYPE    (IDE_LOCAL)  /* ATA 0 logical type */#define ATA0_NUM_DRIVES   (1)          /* ATA 0 number drives present */#define ATA0_INT_LVL      (0x0e)       /* ATA 0 interrupt level */#define ATA0_CONFIG       (ATA_GEO_CURRENT | ATA_PIO_AUTO | \                           ATA_BITS_16     | ATA_PIO_MULTI)#define ATA0_SEM_TIMEOUT  (5)          /* ATA 0 sync. semaphore timeout */#define ATA0_WDG_TIMEOUT  (5)          /* ATA 0 watchdog timer timeout */#define ATA0_SOCKET_TWIN  (0)          /* Socket number (TWIN PCMCIA Card) */#define ATA0_POWER_DOWN   (0)          /* ATA power down mode *//* ATA controller one ataResources[] parameters */#define ATA1_VCC          (5)          /* ATA 1 Vcc (3 or 5 volts) */#define ATA1_VPP          (0)          /* ATA 1 Vpp (5 or 12 volts or 0) */#define ATA1_IO_START0    (0x170)      /* Start I/O Address 0 for ATA 1 */#define ATA1_IO_START1    (0x376)      /* Start I/O Address 1 for ATA 1 */#define ATA1_IO_STOP0     (0x177)      /* Stop I/O Address 0 for ATA 1 */#define ATA1_IO_STOP1     (0x377)      /* Stop I/O Address 1 for ATA 1 */#define ATA1_EXTRA_WAITS  (0)          /* ATA 1 extra wait states (0-2) */#define ATA1_MEM_START    (0)          /* ATA 1 memory start address */#define ATA1_MEM_STOP     (0)          /* ATA 1 memory start address */#define ATA1_MEM_WAITS    (0)          /* ATA 1 memory extra wait states */#define ATA1_MEM_OFFSET   (0)          /* ATA 1 memory offset */#define ATA1_MEM_LENGTH   (0)          /* ATA 1 memory offset */#define ATA1_CTRL_TYPE    (ATA_PCMCIA)  /* ATA 1 logical type */#define ATA1_NUM_DRIVES   (1)          /* ATA 1 number drives present */#define ATA1_INT_LVL      (0x09)       /* ATA 1 interrupt level */#define ATA1_CONFIG       (ATA_GEO_CURRENT | ATA_PIO_AUTO | \                           ATA_BITS_16     | ATA_PIO_MULTI)#define ATA1_SEM_TIMEOUT  (5)          /* ATA 1 sync. semaphore timeout */#define ATA1_WDG_TIMEOUT  (5)          /* ATA 1 watchdog timer timeout */#define ATA1_SOCKET_TWIN  (0)          /* Socket number (TWIN PCMCIA Card) */#define ATA1_POWER_DOWN   (0)          /* ATA 1 power down mode *//* console definitions  */#undef	NUM_TTY#define NUM_TTY       (N_UART_CHANNELS)  /* number of tty channels */#define INCLUDE_PC_CONSOLE                /* PC keyboard and VGA console */#ifdef INCLUDE_PC_CONSOLE#   define PC_CONSOLE           (0)      /* console number */#   define N_VIRTUAL_CONSOLES   (2)      /* shell / application */#endif /* INCLUDE_PC_CONSOLE *//* PS/2 101-key default keyboard type (use PC_XT_83_KBD for 83-key) */#define PC_KBD_TYPE   (PC_PS2_101_KBD)/* memory addresses, offsets, and size constants */#if (SYS_WARM_TYPE == SYS_WARM_BIOS)            /* non-volatile RAM size */#   define NV_RAM_SIZE          (NONE)#else#   define NV_RAM_SIZE          (0x1000)#endif#define USER_RESERVED_MEM       (0)             /* user reserved memory */#define LOCAL_MEM_LOCAL_ADRS    (0x00100000)    /* on-board memory base *//* * LOCAL_MEM_SIZE is the offset from the start of on-board memory to the * top of memory.  If the page size is 2MB or 4MB, write-protected pages * for the MMU directory tables and <globalPageBlock> array are also a * multiple of 2MB or 4MB.  Thus, LOCAL_MEM_SIZE should be big enough to * hold them. */#if  (VM_PAGE_SIZE == PAGE_SIZE_4KB)            /* 4KB page */#   define SYSTEM_RAM_SIZE      (0x00800000)    /* minimum 8MB system RAM */#else   /* PAGE_SIZE_[2/4]MB */                 /* [2/4]MB page */#   define SYSTEM_RAM_SIZE      (0x02000000)    /* minimum 32MB system RAM */#endif  /* (VM_PAGE_SIZE == PAGE_SIZE_4KB) */#define LOCAL_MEM_SIZE          (SYSTEM_RAM_SIZE - LOCAL_MEM_LOCAL_ADRS)/* * Memory auto-sizing is supported when this option is defined. * See sysyPhysMemTop() in the BSP sysLib.c file. */#ifdef	INCLUDE_MMU_P6_36BIT#   undef  LOCAL_MEM_AUTOSIZE#else#   if (CPU == I80486)#      undef  LOCAL_MEM_AUTOSIZE#   else #      define LOCAL_MEM_AUTOSIZE#   endif /* (CPU == I80486) */#endif	/* INCLUDE_MMU_P6_36BIT *//* * The following parameters are defined here and in the BSP Makefile. * They must be kept synchronized.  Any changes made here must be made * in the Makefile and vice versa. */#ifdef	BOOTCODE_IN_RAM#   undef  ROMSTART_BOOT_CLEAR#   define ROM_BASE_ADRS        (0x00008000)    /* base address of ROM */#   define ROM_TEXT_ADRS        (ROM_BASE_ADRS) /* booting from A: or C: */#   define ROM_SIZE             (0x00190000)    /* size of ROM */        /* modify by frank */#else#   define ROM_BASE_ADRS        (0xfff20000)    /* base address of ROM */#   define ROM_TEXT_ADRS        (ROM_BASE_ADRS) /* booting from EPROM */#   define ROM_SIZE             (0x0007fe00)    /* size of ROM */#endif#define RAM_LOW_ADRS            (0x00308000)    /* VxWorks image entry point */#define RAM_HIGH_ADRS           (0x00108000)    /* Boot image entry point *//* * The INCLUDE_ADD_BOOTMEM configuration option enables runtime code which * will add a specified amount of upper memory (memory above physical address * 0x100000) to the memory pool of an image in lower memory.  This option * cannot be used on systems with less than 4MB of memory. * * The default value for ADDED_BOOTMEM_SIZE, the amount of memory to add * to a lower memory image's memory pool, is 2MB.  This value may be increased, * but one must ensure that the pool does not overlap with the downloaded * vxWorks image.  If there is an overlap, then loading the vxWorks runtime * image will corrupt the added memory pool.   The calculation for determining * the ADDED_BOOTMEM_SIZE value is: * *     (RAM_LOW_ADRS + vxWorks image size) < (memTopPhys - ADDED_BOOTMEM_SIZE) * * Where <memTopPhys> is calculated in the BSP sysLib.c file.  This * configuration option corrects SPR 21338. */#define INCLUDE_ADD_BOOTMEM     /* Add upper memory to low memory bootrom */#define ADDED_BOOTMEM_SIZE      (0x00200000)     /* 2MB additional memory *//* power management definitions */#define	VX_POWER_MANAGEMENT	/* define to enable */#define VX_POWER_MODE_DEFAULT   VX_POWER_MODE_AUTOHALT  /* set mode *//* AMP (asymmetric multi processor) definitions */#ifdef	TGT_CPU#   include "configAmp.h"#endif	/* TGT_CPU *//* interrupt mode/number definitions */#include "configInum.h"#ifdef	INCLUDE_IACSFL#   include "iacsfl.h"#endif	/* INCLUDE_IACSFL - iacsfl.h overrides some macros in config.h *//* * defining _WRS_BSP_DEBUG_NULL_ACCESS will disable access to lower  * page in MMU, see sysPhysMemDesc [] and sysPhysMemTop() in sysLib.c  * for more details.  This causes the CPU to generate an exception for  * any NULL pointer access, or any access to lower page of memory.  * VxWorks will suspend the task which made the access. * Note that the MMU must be enabled for this to work. */#define _WRS_BSP_VM_PAGE_OFFSET	(VM_PAGE_SIZE)#undef _WRS_BSP_DEBUG_NULL_ACCESS#ifdef _WRS_BSP_DEBUG_NULL_ACCESS  /* protect NULL access with MMU */#   if (VM_PAGE_SIZE != PAGE_SIZE_4KB) /* works when page size is 4KB */#       error PAGE_SIZE_4KB required to use _WRS_BSP_DEBUG_NULL_ACCESS#   endif /* (VM_PAGE_SIZE == PAGE_SIZE_4KB) */#   if (LOCAL_MEM_LOCAL_ADRS == 0x0)#       undef VEC_BASE_ADRS#       define VEC_BASE_ADRS	((char *) (_WRS_BSP_VM_PAGE_OFFSET * 2))#       undef GDT_BASE_OFFSET#       define GDT_BASE_OFFSET	(0x1000 + (_WRS_BSP_VM_PAGE_OFFSET * 2))#       undef SM_ANCHOR_OFFSET#       define SM_ANCHOR_OFFSET	(0x1100 + (_WRS_BSP_VM_PAGE_OFFSET * 2))#       undef EXC_MSG_OFFSET#       define EXC_MSG_OFFSET	(0x1300 + (_WRS_BSP_VM_PAGE_OFFSET * 2))#       undef FD_DMA_BUF_ADDR#       define FD_DMA_BUF_ADDR	(0x2000 + (_WRS_BSP_VM_PAGE_OFFSET * 2))#       undef FD_DMA_BUF_SIZE#       define FD_DMA_BUF_SIZE	(0x1000)#       undef BOOT_LINE_ADRS#       define BOOT_LINE_ADRS	((char *) (0x1200))#   endif /* (LOCAL_MEM_LOCAL_ADRS == 0x0) */#endif /* _WRS_BSP_DEBUG_NULL_ACCESS */#ifdef __cplusplus}#endif#endif	/* INCconfigh */#if defined(PRJ_BUILD)#   include "prjParams.h"#endif