center;c cl l.Object Name	Description_vxWorks	T{An image with no target shell or target symbol table. Network supportis included and initialized.T}VxWorks.st	T{A fully linked standalone image, including a target basedshell, symbol table, and network interface.  Note that thenetwork interface is not initialized.  There is no WDB agent.T}bootrom_uncmp.bin	T{An uncompressed bootrom image which will run in upper memory by default.T}bootrom.bin	T{A compressed bootrom image which will run in upper memory by default.T}mkboot.o	A VxWorks utility for creating boot disks..TE.SS "Make Targets"The BSP supports the following make targets:.TS Eexpand;cw(1i) cw(2i) clw(1i) lw(2i) l.Image Name	Description	Comments=vxWorks_rom.bin	T{A high memory uncompressed bootable vxWorks image.T}vxWorks.st_rom.bin	T{A high memory compressed bootable vxWorks.st image.T}bootrom.bin	T{A high memory compressed bootrom.T}bootrom_uncmp.bin	T{A high memory uncompressed bootrom.T}vxWorks	The standard "Tornado-style" VxWorks image.vxWorks.st	T{A fully linked standalone vxWorks, including target based shell, symboltable, and network interface.  The network interface is not initialized.There is no WDB agent.T}vxWorks.res_rom	T{A standalone VxWorks image that can be put in ROM.Only the data segment of this ROM image is copied into RAM.T}vxWorks.res_rom_nosym	T{A standalone VxWorks image that can be put in ROM.Only the data segment of this ROM image is copied into RAM.There is no symbol table. T}_.TE.SS "Special Routines"The following routines are specific to this BSP and are availableto the user. The are written in assembly code in sysALib.s. For further details see the reference entries:.TSexpand;sysInByte() | input one byte from I/O spacesysInWord() | input one word from I/O spacesysInLong() | input one long-word from I/O spacesysOutByte() | output one byte to I/O spacesysOutWord() | output one word to I/O spacesysOutLong() | output one long-word to I/O spacesysInWordString() | input word string from I/O spacesysInLongString() | input long string from I/O spacesysOutWordString() | output word string to I/O spacesysOutLongString() | output long string to I/O space.TE.SH "KNOWN PROBLEMS".SS "Tornado 2.2 Problems"As of 1 April, 2002 (Tornado 2.2 Beta), the Intel Architecture stacktrace library, trcLib, has not been updated to handle subroutineprologue code which might be inserted for SSE instruction support.If the Tornado 2.2 compiler is used to build code implementingStreaming SIMD Extension (SSE or SSE2) instructions, then the -mssecompiler flag may be used so that SSE stack operands are aligned onthe proper boundaries.  The compiler currently supports the alignmentof stack variables by inserting subroutine prologue code that thestack trace library does not recognize.  An immediate consequence ofthis is that routines such as tt() may generate exceptions when oneattempts to trace code that has been built with -msse..SS "Validation Test Suite (VTS) Failures"nvRam test: The first test in this suite may fail on the first attempt with a new boot disk.  (NV-RAM is implemented as a file, created on the boot disk on the first write command to NV-RAM.)  Subsequent times through the test suite should succeed.Catastrophic error test: fails as the VTS expectsan exception message but this BSP displays none;however, the BSP correctly recoversby rebooting the target.bootline Test:Bus error test for local error address fails.Bus error test for off-board error address fails.Boot commands test failed as the VTS incorrectly presumes a bigendian architecture..SH "OTHER"The valid auxiliary clock rates are between 2 ticks per second and 2 to the power of 13 ticks per second (2^13 = 8192).Warm booting (reboot) is dependent upon the following parameters (shown withdefault values) in config.h:.CS#define SYS_WARM_BIOS       0   /* warm start from BIOS */#define SYS_WARM_FD         1   /* warm start from FD */#define SYS_WARM_ATA        2   /* warm start from ATA */#define SYS_WARM_TFFS       3   /* warm start from DiskOnChip */#define SYS_WARM_TYPE       SYS_WARM_FD /* warm start device */#define SYS_WARM_FD_DRIVE   0   /* 0 = drive a:, 1 = b: */#define SYS_WARM_FD_TYPE    0   /* 0 = 3.5" 2HD, 1 = 5.25" 2HD */#define SYS_WARM_ATA_CTRL   0   /* controller 0 */#define SYS_WARM_ATA_DRIVE  0   /* 0 = c:, 1 = d: */.CEIf SCSI configuration fails, it may be the result of improper SCSI bus termination. Check termination carefully on all devices, includingthe controller. Note that some deviceshave built in termination that is configured via a jumper.In order to dynamically update the MMU table entries, prior to MMUinitialization, several dummy entries have been added to the end of thememory description table sysPhysMemDesc. This allows PCI deviceconfiguration space, configured by the BIOS, to be properly mapped intothe VxWorks memory map. This is done by sysMmuMapAdd() in sysLib.c.This BSP does not support ISA PnP. Such devices can be supported ifPnP is disabled and the device parameters (IO address, Memory address,IRQ, DMA channel etc) is set to match its BSP driver configuration. Ifthe device uses soft-configuration instead of jumpers, an appropriateutility program, usually available from the device manufacturer,should be used to setup the device parameters.DMA Buffer Alignment and cacheLibIf you write device drivers that use Intel 8237 direct memory access into buffers obtained from cacheLib, the buffers must be aligned on a 64KB boundary and be in the lower memory..SS "Non Intel X86 Processor"sysCpuProbe() uses CPUID instruction to identify processor and featuresfor Intel processors.  Here is what said in the application note AP-485 "Intel Processor Identification and the CPUID Instruction":  - Use the CPUID feature flags in your applications to determine which    processor features are supported.  By using the CPUID feature flags    to determine processor features, your software can detect and avoid    incompatibilities introduced by the addition or removal of processor    features.  - Do not assume that a given processor family or model has any specific    feature.  For example, do not assume the family value 5 (Pentium    processor) means there is a FPU on-chip.  Use the feature flags for    this determination.  - Do not assume processors with higher family or model numbers have    all the features of a processor with a lower family or model    number.  For example, a processor with a family value of 6 (P6 family    processor) may not necessarily have all the features of a processor    with a family value of 5.For non Intel X86 processors, there are two ways to bypass this CPUIDidentification mechanism.  The static configuration is one, and the dynamic runtime checking is another.  Former is to use the build parameter INCLUDE_CPU_PROBE, and to set the processor type manually with X86CPU_DEFAULT in config.h.  The latter is to execute CPUID and check the vendor ID string "GenuineIntel" in sysCpuProbe().  If there is no match, the processor type is set to X86CPU_DEFAULT.  In both cases, the default processor type X86CPU_DEFAULT(PENTIUM) is set and CPUID feature bits stay zero that prevent enabling PENTIUM specific features which non Intel X86 processors may not have.  If the processor does not have CR4 register,like Intel 80486, comment out the ARCH_CR4_INIT macro in romInit.s and sysALib.s.  The CR4 is introduced in the P5(Pentium) architecture.  TheAPI vxCr4Get() and vxCr4Set() checks sysProcessor, and do nothing if itis pre P5(Pentium) architecture.  A targeting BSP for non Intel X86 processor is pcPentium.  For now, non Intel X86 processor specific features are not supported..SS "P5 (Pentium), P6 (PentiumPro, II, III), and P7 (Pentium4) family processor"Following features are supported for P5 (Pentium), P6 (PentiumPro, II, III), and P7 (Pentium4) family processor, and they are enabled in sysHwInit() depending upon the feature flags obtained by the CPUID instruction.  See pentiumLib for more details of these features..IP "Memory Type Range Registers (MTRRs)" If INCLUDE_MTRR_GET is defined, contents of the MTRRS are copied to the sysMtrr[] table.  Otherwise it sets the contents of sysMtrr[] to the MTRRs..IP "Performance Monitoring Counter (PMC)"This is an optional feature configured by INCLUDE_PMC macro.  In this release,Pentium4's PMC is not supported yet..IP "Machine Check Architecture (MCA)"This is enabled in pentiumMcaEnable() in sysHwInit() if the MCA is supportedby the processor..IP "Time Stamp Counter (TSC)"If INCLUDE_TIMESTAMP_TSC is defined, on-chip TSC is used for the time stamp driver.  PENTIUM_TSC_FREQ specifies its frequency.If it is defined to zero, the frequency is automatically detected..IP "Enhanced MMU"The enhanced MMU is included by defining INCLUDE_MMU_P6_32BIT orINCLUDE_MMU_P6_36BIT macro.  With INCLUDE_MMU_P6_32BIT, 4KB-page and 4MB-page are supported.  With INCLUDE_MMU_P6_36BIT, 4KB-page and 2MB-page are supported.  The page size is configurable by VM_PAGE_SIZE macro.  Two architecture specific VM library APIsare provided and linked in automatically.  For bundled VM library,they are vmBaseArch32Map() and vmBaseArch32Translate().For unbundled VM library VxVMI, they are vmArch32Map() and vmArch32Translate().  Their 36 bit version are also available.Two new memory attribute macros, VM_STATE_WBACK and VM_STATE_GLOBAL, are added.  VM_STATE_WBACK (clear PWT bit) and VM_STATE_WBACK_NOT (set PWT bit)represents the cache mode of a page.VM_STATE_GLOBAL (set GLOBAL bit) and VM_STATE_GLOBAL_NOT (clearGLOBAL bit) represents the global characteristics of a page..IP "Advanced Programmable Interrupt Controller (APIC)"Intel P6 (PentiumPro, II, and III) and P7 (Pentium4) family processor's APIC/xAPIC is supported in either Virtual Wire Mode (defineVIRTUAL_WIRE_MODE in config.h) or Symmetric IO Mode (define SYMMETRIC_IO_MODE in config.h).  If neither of them is defined,VxWorks uses a mode that is set up by BIOS, which could be VirtualWire Mode or PIC Mode.  Only Local APIC/xAPIC is used in Virtual Wire Mode, both Local APIC/xAPIC and IO APIC/xAPIC are used in Symmetric IO Mode..IP "Data Cache Mode"CACHE_COPYBACK data cache mode is default for Pentium. It uses Write Back data cache mode with the generic MMU libraryfor X86 architecture.CACHE_COPYBACK and CACHE_SNOOP_ENABLE is default for P6 (PentiumPro,II, III) and P7 (Pentium4) family processors.CACHE_COPYBACK has no effect to the MMU library with INCLUDE_MMU_PENTIUMPRO defined, that support page basis Write Back/Write Through cache mode.CACHE_SNOOP_ENABLE respects MESI cache protocol and doesn't invokethe WBINVD (write back and invalidate cache) instruction in theflush routine in the cache library..SS "MTRR"This table shows effective memory type depending on MTRR, PCD, andPWT setting..TS Eexpand;c c c cc c c cl l l l.MTRR mem type	PCD value	PWT value	Effective mem type_UC	X	X	UCWC	0	0	WC	0	1	WC	1	0	WC	1	1	UCWT	0	X	WT	1	X	UCWP	0	0	WP	0	1	WP	1	0	UC	1	1	UCWB	0	0	WB	0	1	WT	1	X	UC_.TEThis table shows MTRR memory types and their properties..TS Eexpand;c c c c cc c c c cl l l l l.	Cacheable in		Allows	Memory	L1 and L2	Writeback	Speculative	OrderingMnemonic	Caches	Cacheable	Reads	Model_UC	No	No	No	Strong OrderingWC	No	No	Yes	Weak OrderingWT	Yes	No	Yes	Speculative				Processor OrderingWP	Yes for reads,	No	Yes	Speculative	No for writes			Processor OrderingWB	Yes	Yes	Yes	Speculative				Processor Ordering_.TE.SS "DEBUGGING NULL ACCESSES with the MMU"The macro _WRS_BSP_DEBUG_NULL_ACCESS may be defined in config.h to debug NULL accesses in code.  Marking the lower page of RAM invalid in the MMU causes any code access to NULL (or any offset from NULL up to page size) to throw an exception, suspending the offending task.  Making it very easy to debug the NULL access with lkAddr(), and l() from the shell.Consider this simple errant code which reads from a NULL pointer:.CS/* tmp.c */#include "vxWorks.h"UINT32 tmpFunc    (