if (adr[0] & 0x1)        return (ERROR);     return OK;    }/*************************************************************************** * sys543eepromCheckSum - calculate checksum ** This routine perform EEPROM checksum** RETURNS: N/A*/LOCAL STATUS sys543eepromCheckSum    (    int    unit    )    {    UINT16 checkSum = 0 ;    UINT32 ix;    for (ix = 0; ix < EEPROM_WORD_SIZE; ix++)         checkSum += sys543eepromReadWord (unit, ix);     if (checkSum == (UINT16)EEPROM_SUM)        return OK;     return ERROR;    }/***************************************************************************** sys544PhyPreInit -- Init 82544's specific PHY regs before link setup** This routine initializes some 82544's PHY regs before set up link* Basically, it fixed short cable/backplane problem, Errata 21** RETURN: N/A*/LOCAL void sys544PhyPreInit    (    PHY_INFO * pPhyInfo     /* PHY's info structure pointer */    )    {    UINT16 regVal;          /* register value */    UINT16 phyId1;          /* phy Id 1 */    UINT16 phyId2;          /* phy ID 2 */    UINT32 retVal;          /* return value */    UINT32 phyOui = 0;      /* PHY's manufacture ID */    UINT32 phyMode;         /* PHY mode number */    UINT8  phyAddr;         /* PHY's bus number */    phyAddr = pPhyInfo->phyAddr;     MII_READ (phyAddr, MII_PHY_ID1_REG, &phyId1, retVal);       MII_READ (phyAddr, MII_PHY_ID2_REG, &phyId2, retVal);    phyOui =  phyId1 << 6 | phyId2 >> 10;    phyMode = (phyId2 & MII_ID2_MODE_MASK) >> 4;    if (phyOui == INTEL_82544PHY_OUI_ID && (phyMode == INTEL_82544PHY_MODEL))        {        regVal = 0x0004;         MII_WRITE (phyAddr, 29, 0x4, retVal);        MII_READ (phyAddr, 30, &regVal, retVal);        regVal |= 0x0200;         MII_WRITE (phyAddr, 30, regVal, retVal);        }    }/**************************************************************************** sys543PhySpecRegsInit - Initialize PHY specific registers** This routine initialize PHY specific registers** RETURN: N/A*/LOCAL void sys543PhySpecRegsInit    (    PHY_INFO * pPhyInfo,    /* PHY's info structure pointer */    UINT8      phyAddr      /* PHY's bus number */    )    {    UINT16 regVal;          /* register value */    UINT16 phyId1;          /* phy Id 1 */    UINT16 phyId2;          /* phy ID 2 */    UINT32 retVal;          /* return value */    UINT32 phyOui = 0;      /* PHY's manufacture ID */    UINT32 phyMode;         /* PHY mode number */    /* Intel Pro1000T adaptor uses Alaska transceiver */    /* read device ID to check Alaska chip available */    MII_READ (phyAddr, MII_PHY_ID1_REG, &phyId1, retVal);        MII_READ (phyAddr, MII_PHY_ID2_REG, &phyId2, retVal);           phyOui =  phyId1 << 6 | phyId2 >> 10;    phyMode = (phyId2 & MII_ID2_MODE_MASK) >> 4;    if (phyOui == MARVELL_OUI_ID && (phyMode == MARVELL_ALASKA_88E1000 ||                                      phyMode == MARVELL_ALASKA_88E1000S))        {         /* This is actually a Marvell Alaska 1000T transceiver */         /* disable PHY's interrupt */                  MII_READ (phyAddr, ALASKA_INT_ENABLE_REG, &regVal, retVal);         regVal = 0;         MII_WRITE (phyAddr, ALASKA_INT_ENABLE_REG, regVal, retVal);         /* CRS assert on transmit */         MII_READ (phyAddr, ALASKA_PHY_SPEC_CTRL_REG, &regVal, retVal);         regVal |= ALASKA_PSCR_ASSERT_CRS_ON_TX;         MII_WRITE (phyAddr, ALASKA_PHY_SPEC_CTRL_REG, regVal, retVal);        /* set the clock rate when operate in 1000T mode */         MII_READ (phyAddr, ALASKA_EXT_PHY_SPEC_CTRL_REG, &regVal, retVal);         regVal |= ALASKA_EPSCR_TX_CLK_25;         MII_WRITE (phyAddr, ALASKA_EXT_PHY_SPEC_CTRL_REG, regVal, retVal);        }    else if (phyOui == INTEL_82544PHY_OUI_ID &&             (phyMode == INTEL_82544PHY_MODEL))        {         /* This is INTEL 82544GC/EI internal PHY */         /* disable PHY's interrupt */                  MII_READ (phyAddr, INTEL_82544PHY_INT_ENABLE_REG, &regVal, retVal);         regVal = 0;         MII_WRITE (phyAddr, INTEL_82544PHY_INT_ENABLE_REG, regVal, retVal);         /* CRS assert on transmit */         MII_READ (phyAddr, INTEL_82544PHY_PHY_SPEC_CTRL_REG,                    &regVal, retVal);         regVal |= INTEL_82544PHY_PSCR_ASSERT_CRS_ON_TX;         MII_WRITE (phyAddr, INTEL_82544PHY_PHY_SPEC_CTRL_REG,                    regVal, retVal);        /* set the TX_CLK rate when operate in 1000T mode */         MII_READ (phyAddr, INTEL_82544PHY_EXT_PHY_SPEC_CTRL_REG,                    &regVal, retVal);         regVal |= INTEL_82544PHY_EPSCR_TX_CLK_25;         MII_WRITE (phyAddr, INTEL_82544PHY_EXT_PHY_SPEC_CTRL_REG,                    regVal, retVal);        /* INTEL PHY's bug fixing ... */         MII_WRITE (phyAddr, 29, 0x5, retVal);        MII_READ (phyAddr, 30, &regVal, retVal);        regVal |= 0x100;        MII_WRITE (phyAddr, 30, regVal, retVal);               }             /* other PHYS .... */     }/******************************************************************************* sys543IntAck - acknowledge an 8254x interrupt** This routine performs any 8254x interrupt acknowledge that may be* required.  This typically involves an operation to some interrupt* control hardware.** This routine gets called from the 82543 driver's interrupt handler.** This routine assumes that the PCI configuration information has already* been setup.** RETURNS: OK, or ERROR if the interrupt could not be acknowledged.*/LOCAL STATUS sys543IntAck    (    int    unit        /* unit number */    )    {    return (OK);    }/******************************************************************************* sys543IntEnable - enable 8254x chip interrupts** This routine enables 8254x interrupts.  This may involve operations on* interrupt control hardware.** The 8254x driver calls this routine throughout normal operation to terminate* critical sections of code.** This routine assumes that the PCI configuration information has already* been setup.** RETURNS: OK, or ERROR if interrupts could not be enabled.*/LOCAL STATUS sys543IntEnable    (    int    unit        /* unit number */    )    {    return (OK);    }/******************************************************************************* sys543IntDisable - disable 8254x chip interrupts** This routine disables 8254x interrupts.  This may involve operations on* interrupt control hardware.** The 8254x driver calls this routine throughout normal operation to enter* critical sections of code.** This routine assumes that the PCI configuration information has already* been setup.** RETURNS: OK, or ERROR if interrupts could not be disabled.*/LOCAL STATUS sys543IntDisable    (    int    unit        /* unit number */    )    {    return (OK);    }/******************************************************************************* sys543Show - shows 8254x chip configuration ** This routine shows (Intel Pro 1000F/T/XT/XF) adapter configuration ** RETURNS: N/A*/void sys543Show    (    int    unit        /* unit number */    )    {    int    ix;    PCI_BOARD_RESOURCE * pRsrc;    GEI_RESOURCE *       pReso;    if (unit >= geiUnits)        {        printf ("gei device %d is not available\n", unit);        return;        }     pRsrc = &geiPciResources [unit];    pReso = (GEI_RESOURCE *)(pRsrc->pExtended);    if (pRsrc->boardType == PRO1000_543_BOARD)        printf ("********* Intel PRO1000 82543GC Based Adapter ***********\n");    else if (pRsrc->boardType == PRO1000_544_BOARD)        printf ("********* Intel PRO1000 82544GC/EI based Adapter ********\n");    else if (pRsrc->boardType == PRO1000_546_BOARD)        printf ("********* Intel 82540/82545/82546EB based Adapter ********\n");    else        printf ("********* UNKNOWN Adaptor ************ \n");     printf ("  CSR PCI Membase address = 0x%x\n", pReso->memBaseLow);     printf ("  Flash PCI Membase address = 0x%x\n", pReso->flashBase);    printf ("  PCI bus no.= 0x%x, device no.= 0x%x, function no.= 0x%x\n",              pRsrc->pciBus, pRsrc->pciDevice, pRsrc->pciFunc);    printf ("  IRQ = %d\n", pRsrc->irq);      if (pReso->iniStatus == ERROR)        return;    printf ("  Adapter Ethernet Address");    for (ix = 0; ix < 6; ix ++)        printf (":%2.2X", (UINT32)pReso->enetAddr[ix]);    printf ("\n");    printf ("  EEPROM Initialization Control Word 1 = 0x%4.4X\n",             pReso->eeprom_icw1);    printf ("  EEPROM Initialization Control Word 2 = 0x%4.4X\n",             pReso->eeprom_icw2);    printf ("*********************************************\n");    }/********************************************************************************* sysGeiDevToType - convert PCI Vendor and Device IDs to a device type** Given <vendorId>, <deviceId>, and <revisionId> values read from PCI Vendor* and Device ID registers in PCI configuration space, this routine will* attempt to map the IDs to an 8254x device type value.** RETURNS:* A board type value which will be one of** .IP* PRO1000_543_BOARD* .IP* PRO1000_544_BOARD* .IP* PRO1000_546_BOARD* .LP** BOARD_TYPE_UNKNOWN will be returned if the Device ID does not map to* a supported board type.** NOMANUAL*/LOCAL UINT32 sysGeiDevToType    (    UINT32 vendorId,    /* specifies a PCI Vendor ID value */    UINT32 deviceId,    /* specifies a PCI Device ID value */    UINT8  revisionId   /* specifies a PCI Revision ID value */    )    {    /* At the moment, we are only supporting vendor Intel */    if (vendorId == PRO1000_PCI_VENDOR_ID)        {        switch (deviceId)            {            case PRO1000_543_PCI_DEVICE_ID_T:            case PRO1000_543_PCI_DEVICE_ID_FT:                return (PRO1000_543_BOARD);            case PRO1000_544_PCI_DEVICE_ID_XT:            case PRO1000_544_PCI_DEVICE_ID_XF:            case PRO1000_544_PCI_DEVICE_ID_GC:                return (PRO1000_544_BOARD);                        case PRO1000_540_PCI_DEVICE_ID_XT:            case PRO1000_545_PCI_DEVICE_ID_XT:            case PRO1000_546_PCI_DEVICE_ID_XT:            case PRO1000_545_PCI_DEVICE_ID_MF:            case PRO1000_546_PCI_DEVICE_ID_MF:                return (PRO1000_546_BOARD);            }        }    return (BOARD_TYPE_UNKNOWN);    }#endif /* INCLUDE_GEI8254X_END */