#ifndef __HAL_H__
#define __HAL_H__

#include "mcf5xxx.h"
#include "m523xevb.h" 

#ifdef __cplusplus
 extern "C" {
#endif

#define 	HC_COMMAND_PORT 			(*(volatile uint16 *)0x12000002)
#define 	HC_DATA_PORT  				(*(volatile uint16 *)0x12000000)

/* 32 bit OHCI register */

#define		HC_REVISION					(0x00)		/* HC控制和狀態寄存器 */
#define		HC_CONTROL					(0x01)
#define		HC_COMMAMDSTATUS			(0x02)
#define		HC_INTERRUPTSTATUS			(0x03)
#define 	HC_INTERRUPTENABLE			(0x04)
#define 	HC_INTERRUPTDISABLE			(0x05)
#define		HC_FMINTERVAL				(0x0D)		/* HC幀計數器寄存器 */
#define 	HC_FMREMAINING				(0x0E)
#define		HC_FMNUMBER					(0x0F)
#define		HC_LSTHRESHOLD				(0x11)
#define		HC_RHDESCRIPTORA			(0x12)		/* HC根集線器寄存器 */
#define		HC_RHDESCRIPTORB			(0x13)
#define		HC_RHSTATUS					(0x14)
#define		HC_RHPORTSTATUS1			(0x15)
#define		HC_RHPORTSTATUS2			(0x16)

/* 16 bit ISP1362 register */

#define		HC_HARDWARECONFIG			(0x20)		/* HC DMA中斷控制寄存器 */
#define		HC_DMACONFIG				(0x21)
#define		HC_TRANSFERCOUNTER			(0x22)
#define		HC_uPINTERRUPT				(0x24)
#define		HC_uPINTERRUPTENABLE		(0x25)
#define		HC_CHIPID					(0x27)		/* HC雜項寄存器 */
#define		HC_SCRATCH					(0x28)
#define		HC_SOFTWARERESET			(0x29)

#define		HC_BUFFERSTATUS				(0x2C)		/* HC緩沖區RAM寄存器 */
#define     Hc_DirectAddressLength		(0x32)		/*32bit*/									
#define 	Hc_DirectAddressDataPort	(0x45)

#define		Hc_ATLBufferSize			(0x34)
#define		HC_ATLBUFFERPORT			(0x44)
#define     Hc_ATLBlkSize				(0x54)
#define     Hc_ATLPTDDoneMap   			(0x1B)		/*32bit*/
#define     Hc_ATLPTDSkipMap   			(0x1C)		/*32bit*/
#define     Hc_ATLLastPTD   			(0x1D)		/*32bit*/
#define     Hc_ATLCurrentActivePTD		(0x1E)
#define     Hc_ATLPTDDoneThresholdCount   		(0x51)
#define     Hc_ATLPTDDoneThresholdTimeOut		(0x52)

#define     Hc_ISTLBufferSize           (0x30)
#define     Hc_INTLBufferSize           (0x33)

/****************************************************************************/

#define     Hc_ATLBufferLen             (0x0A00)
#define     Hc_ATLBlkLen                (0x0200)//(0x0040)
#define     Hc_PairedATLBufLen          (0x250)
#define     Hc_PairedLen                (0x500)
#define     Hc_PTDLen                   (8 + Hc_ATLBlkLen)
#define     Hc_ISTLBufferLen            (0x0000)
#define     Hc_INTLBufferLen            (0x0000)

#define     ATLSTARTADDR                ((Hc_ISTLBufferLen << 1) + Hc_INTLBufferLen)

/****************************************************************************/

#define		SOF								0x0001
#define		OPR								0x0010
#define		MIE								0x80000000
#define		RHSC							0x00000040
#define		SF								0x00000004
#define		RWE_RWC							0x00000600
#define		FRAMEINTERVAL					0x2EDF
#define		FSLARGESTDATAPACKET				0x2778
#define		POWERONTOPOWERGOODTIME			50

/*															
 * HcuPInterrupt
 */
#define 	SOFITLInt						(1 << 0)
#define 	ATLInt							(1 << 1)
#define 	AllEOTInterrupt					(1 << 2)
#define 	OPR_Reg							(1 << 4)
#define 	HCSuspended						(1 << 5)
#define 	ClkReady						(1 << 6)

/*
 * masks used with interrupt registers:
 * HcInterruptStatus (intrstatus)
 * HcInterruptEnable (intrenable)
 * HcInterruptDisable (intrdisable)
 */
#define 	OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
#define 	OHCI_INTR_SF	(1 << 2)	/* start frame */
#define 	OHCI_INTR_RD	(1 << 3)	/* resume detect */
#define 	OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
#define 	OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
#define 	OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
#define 	OHCI_INTR_ATD	(1 << 7)	/* scheduling overrun */
#define 	OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */

/*********************************************************************/
#define     WordSwap(x)     (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8))
#define     asm             _ASMLINE 


/*HcHardwareConfiguration*/
#define 	InterruptPinEnable 		(1 << 0)
#define 	InterruptPinTrigger 	(1 << 1)
#define 	InterruptOutputPolarity	(1 << 2)
#define 	DataBusWidth16			(1 << 3)
#define 	DREQOutputPolarity		(1 << 5)
#define 	DACKInputPolarity		(1 << 6)
#define 	EOTInputPolarity		(1 << 7)
#define 	DACKMode				(1 << 8)
#define 	AnalogOCEnable			(1 << 10)
#define 	SuspendClkNotStop		(1 << 11)
#define 	DownstreamPort15KRSel	(1 << 12)

typedef struct _SFLAGS
{		
		uint8 SLAVE_ATTACHED	;
		uint8 SLAVE_REMOVED		;	/* device unplugged during data transfer */
		uint8 SLAVE_FOUND	    ;	/* Slave USB device found */
		uint8 SLAVE_ENUMERATED	;	/* slave USB device enumeration done */
		uint8 SLAVE_ONLINE		;
		uint8 SLAVE_MASSDEVICE  ;	
		uint8 ERROR			;	
		uint8 bak    		;
		
} SFLAGS;

#ifndef TRUE
  #define TRUE 0x5A
#endif

#ifndef FALSE
  #define FALSE 0
#endif

/******************************************************************************/
uint16 ISP1362Reg16Read(uint16 regaddr);
void ISP1362Reg16Write(uint16 regaddr, uint16 data);
uint32 ISP1362Reg32Read(uint16 regaddr);
void ISP1362Reg32Write(uint16 regaddr, uint32 data);

void ReadATLIndirect(uint16 * pBufAddr, uint16 TotalBytes);
void WriteATLIndirect(uint16 * pBufAddr, uint16 TotalBytes);
void ReadATLDirect(uint16 * pBufAddr, uint16 StartAddr, uint16 TotalBytes);
void WriteATLDirect(uint16 * pWBufAddr, uint16 StartAddr, uint16 TotalBytes);
void SwapWriteATLDirect(uint16 * pBufAddr, uint16 StartAddr, uint16 TotalBytes);
void ActiveATLPTD(void);
void ResetPairedPTD(void);

void ISP1362SuspendDevice(void);
void ISP1362SetDeviceInOperational(void);

//uint16 WordSwap(uint16 input);
uint16 LSwapuint16(uint16 dData1,uint16 dData2);
uint32 LSwapuint32(uint32 dData1,uint32 dData2,uint32 dData3,uint32 dData4);

void ISP1362SoftwareReset(void);

//void Delay_100ns(void);
void Delay_100ns(uint32 t);
void Delay_1ms  (uint32 t);

void ISP1362Init(void);
int8 CheckDevice();

#ifdef __cplusplus
}
#endif

#endif