?? merge.mdl
字號(hào):
Model {
Name "merge"
Version 4.00
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovNameIncrementing off
CovHtmlReporting on
BlockNameDataTip off
BlockParametersDataTip on
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Tue Nov 27 10:11:08 2001"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Tue Nov 27 11:17:12 2001"
ModelVersionFormat "1.%<AutoIncrement:4>"
ConfigurationManager "none"
SimParamPage "Solver"
StartTime "0.0"
StopTime "10.0"
SolverMode "Auto"
Solver "ode45"
RelTol "1e-3"
AbsTol "auto"
Refine "1"
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
MaxOrder 5
OutputOption "RefineOutputTimes"
OutputTimes "[]"
LoadExternalInput off
ExternalInput "[t, u]"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
LoadInitialState off
InitialState "xInitial"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
LimitDataPoints off
MaxDataPoints "1000"
Decimation "1"
AlgebraicLoopMsg "warning"
MinStepSizeMsg "warning"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
InheritedTsInSrcMsg "warning"
SingleTaskRateTransMsg "none"
MultiTaskRateTransMsg "error"
IntegerOverflowMsg "warning"
CheckForMatrixSingularity "none"
UnnecessaryDatatypeConvMsg "none"
Int32ToFloatConvMsg "warning"
SignalLabelMismatchMsg "none"
LinearizationMsg "none"
VectorMatrixConversionMsg "none"
SfunCompatibilityCheckMsg "none"
BlockPriorityViolationMsg "warning"
ArrayBoundsChecking "none"
ConsistencyChecking "none"
ZeroCross on
Profile off
SimulationMode "normal"
RTWSystemTargetFile "grt.tlc"
RTWInlineParameters off
RTWRetainRTWFile off
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
TLCProfiler off
TLCDebug off
TLCCoverage off
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "oneshot"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect off
ExtModeLogAll on
OptimizeBlockIOStorage on
BufferReuse on
ParameterPooling on
BlockReductionOpt off
BooleanDataType off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "merge"
Location [12, 315, 382, 573]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
ReportName "simulink-default.rpt"
Block {
BlockType DiscretePulseGenerator
Name "Discrete Pulse\nGenerator"
Description "Enable signal"
Position [30, 89, 85, 121]
ShowName off
AttributesFormatString "Enable"
FontName "Arial"
FontSize 12
FontWeight "bold"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
SampleTime "4"
VectorParams1D on
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [1, 1]
Position [122, 130, 168, 160]
Orientation "down"
NamePlacement "alternate"
ShowName off
FontName "Arial"
FontSize 12
Operator "NOT"
Inputs "1"
}
Block {
BlockType Merge
Name "Merge"
Ports [2, 1]
Position [235, 98, 285, 142]
ShowName off
FontName "Arial"
FontSize 12
Inputs "2"
InitialOutput "[]"
AllowUnequalInputPortWidths off
InputPortOffsets "[]"
}
Block {
BlockType Reference
Name "Repeating\nSequence"
Ports [0, 1]
Position [30, 186, 85, 224]
ShowName off
AttributesFormatString "sawtooth"
FontName "Arial"
FontSize 12
FontWeight "bold"
SourceBlock "simulink3/Sources/Repeating\nSequence"
SourceType "Repeating table"
rep_seq_t "[0 1]"
rep_seq_y "[0 2]"
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [305, 98, 350, 142]
FontName "Arial"
FontSize 12
FontWeight "bold"
Floating off
Location [393, 294, 710, 592]
Open on
NumInputPorts "1"
TickLabels "on"
ZoomMode "on"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
Grid "on"
TimeRange "20"
YMin "-1.5"
YMax "2"
SaveToWorkspace off
SaveName "ScopeData"
DataFormat "Array"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType Sin
Name "Sine Wave"
Position [30, 36, 85, 74]
ShowName off
AttributesFormatString "sin "
FontName "Arial"
FontSize 12
FontWeight "bold"
Amplitude "1"
Frequency "pi"
Phase "0"
SampleTime "0"
VectorParams1D on
}
Block {
BlockType SubSystem
Name "Subsystem"
Tag "MergeExample"
Description "sys1"
Ports [1, 1, 1]
Position [115, 36, 175, 74]
NamePlacement "alternate"
ShowName off
AttributesFormatString "sys1"
FontName "Arial"
FontSize 12
FontWeight "bold"
ShowPortLabels on
TreatAsAtomicUnit on
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
MaskType "sys1"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "Subsystem"
Location [478, 207, 709, 319]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Inport
Name "U"
Position [15, 68, 45, 82]
FontSize 12
FontWeight "bold"
Port "1"
Interpolate on
}
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [75, 15, 121, 50]
FontSize 12
FontWeight "bold"
StatesWhenEnabling "reset"
ShowOutputPort off
}
Block {
BlockType "S-Function"
Name "S-Function"
Ports []
Position [135, 15, 195, 45]
FontSize 12
FontWeight "bold"
FunctionName "mergefcn"
PortCounts "[]"
SFunctionModules "''"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
}
Block {
BlockType Outport
Name "Y"
Position [175, 68, 205, 82]
FontSize 12
FontWeight "bold"
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Line {
SrcBlock "U"
SrcPort 1
DstBlock "Y"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Subsystem1"
Tag "MergeExample"
Description "sys2"
Ports [1, 1, 1]
Position [115, 183, 180, 227]
ShowName off
AttributesFormatString "sys2"
FontName "Arial"
FontSize 12
FontWeight "bold"
ShowPortLabels on
TreatAsAtomicUnit on
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
System {
Name "Subsystem1"
Location [451, 371, 810, 541]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Inport
Name "U"
Position [70, 103, 100, 117]
Port "1"
Interpolate on
}
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [150, 24, 188, 55]
StatesWhenEnabling "reset"
ShowOutputPort off
}
Block {
BlockType "S-Function"
Name "S-Function"
Ports []
Position [235, 25, 295, 55]
FunctionName "mergefcn"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType Outport
Name "Y"
Position [230, 103, 260, 117]
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Line {
SrcBlock "U"
SrcPort 1
DstBlock "Y"
DstPort 1
}
}
}
Line {
SrcBlock "Sine Wave"
SrcPort 1
DstBlock "Subsystem"
DstPort 1
}
Line {
SrcBlock "Subsystem"
SrcPort 1
Points [30, 0; 0, 55]
DstBlock "Merge"
DstPort 1
}
Line {
SrcBlock "Subsystem1"
SrcPort 1
Points [25, 0; 0, -75]
DstBlock "Merge"
DstPort 2
}
Line {
SrcBlock "Discrete Pulse\nGenerator"
SrcPort 1
Points [55, 0; 0, 10]
Branch {
DstBlock "Logical\nOperator"
DstPort 1
}
Branch {
DstBlock "Subsystem"
DstPort enable
}
}
Line {
SrcBlock "Repeating\nSequence"
SrcPort 1
DstBlock "Subsystem1"
DstPort 1
}
Line {
SrcBlock "Merge"
SrcPort 1
DstBlock "Scope"
DstPort 1
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
DstBlock "Subsystem1"
DstPort enable
}
}
}
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