?? bsp.txt
字號:
; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 903] for uVision
; commandline ArmCC [--debug -c --asm --interleave -obsp.o --depend=bsp.d --device=DARMP --apcs=interwork -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\ARM\Generic\RVMDK -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\ARM\RVMDK -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uCOSView\Source -I..\..\..\..\..\uCOSView\Ports\ARM7\LPC2468\IAR -Id:\Keil\ARM\INC\Philips ..\BSP\bsp.c]
ARM
AREA ||.text||, CODE, READONLY, ALIGN=2
BSP_CPU_ClkFreq PROC
;;;242 CPU_INT32U BSP_CPU_ClkFreq (void)
;;;243 {
000000 e92d47f0 PUSH {r4-r10,lr}
;;;244 CPU_INT32U msel;
;;;245 CPU_INT32U nsel;
;;;246 CPU_INT32U fin;
;;;247 CPU_INT32U pll_clk_feq; /* When the PLL is enabled, this is Fcco */
;;;248 CPU_INT32U clk_div;
;;;249 CPU_INT32U clk_freq;
;;;250
;;;251
;;;252 switch (CLKSRCSEL & 0x03) { /* Determine the current clock source */
000004 e59f0e64 LDR r0,|L1.3696|
000008 e590010c LDR r0,[r0,#0x10c]
00000c e2100003 ANDS r0,r0,#3
000010 0a000004 BEQ |L1.40|
000014 e3500001 CMP r0,#1
000018 0a000005 BEQ |L1.52|
00001c e3500002 CMP r0,#2
000020 1a000009 BNE |L1.76|
000024 ea000005 B |L1.64|
|L1.40|
;;;253 case 0:
000028 e1a00000 MOV r0,r0
;;;254 fin = IRC_OSC_FRQ;
00002c e59f6e40 LDR r6,|L1.3700|
;;;255 break;
000030 ea000008 B |L1.88|
|L1.52|
;;;256
;;;257 case 1:
000034 e1a00000 MOV r0,r0
;;;258 fin = MAIN_OSC_FRQ;
000038 e59f6e34 LDR r6,|L1.3700|
;;;259 break;
00003c ea000005 B |L1.88|
|L1.64|
;;;260
;;;261 case 2:
000040 e1a00000 MOV r0,r0
;;;262 fin = RTC_OSC_FRQ;
000044 e3a06902 MOV r6,#0x8000
;;;263 break;
000048 ea000002 B |L1.88|
|L1.76|
;;;264
;;;265 default:
00004c e1a00000 MOV r0,r0
;;;266 fin = IRC_OSC_FRQ;
000050 e59f6e1c LDR r6,|L1.3700|
;;;267 break;
000054 e1a00000 MOV r0,r0
|L1.88|
000058 e1a00000 MOV r0,r0
;;;268 }
;;;269
;;;270 if ((PLLSTAT & (1 << 25)) > 0) { /* If the PLL is currently enabled and connected */
00005c e59f0e0c LDR r0,|L1.3696|
000060 e5900088 LDR r0,[r0,#0x88]
000064 e3100402 TST r0,#0x2000000
000068 0a00000f BEQ |L1.172|
;;;271 msel = (CPU_INT32U)(PLLSTAT & 0x3FFF) + 1; /* Obtain the PLL multiplier */
00006c e59f0dfc LDR r0,|L1.3696|
000070 e5900088 LDR r0,[r0,#0x88]
000074 e1a00900 LSL r0,r0,#18
000078 e1a00920 LSR r0,r0,#18
00007c e2804001 ADD r4,r0,#1
;;;272 nsel = (CPU_INT32U)((PLLSTAT >> 16) & 0x0F) + 1; /* Obtain the PLL divider */
000080 e59f0de8 LDR r0,|L1.3696|
000084 e5900088 LDR r0,[r0,#0x88]
000088 e3a0100f MOV r1,#0xf
00008c e0010820 AND r0,r1,r0,LSR #16
000090 e2805001 ADD r5,r0,#1
;;;273 pll_clk_feq = (2 * msel * fin / nsel); /* Compute the PLL output frequency */
000094 e1a01084 LSL r1,r4,#1
000098 e0000691 MUL r0,r1,r6
00009c e1a01005 MOV r1,r5
0000a0 ebfffffe BL __aeabi_uidivmod
0000a4 e1a07000 MOV r7,r0
0000a8 ea000000 B |L1.176|
|L1.172|
;;;274 } else {
;;;275 pll_clk_feq = (fin); /* The PLL is bypassed */
0000ac e1a07006 MOV r7,r6
|L1.176|
;;;276 }
;;;277
;;;278 clk_div = (CPU_INT08U)(CCLKCFG & 0x0F) + 1; /* Obtain the CPU core clock divider */
0000b0 e59f0db8 LDR r0,|L1.3696|
0000b4 e5900104 LDR r0,[r0,#0x104]
0000b8 e200000f AND r0,r0,#0xf
0000bc e2808001 ADD r8,r0,#1
;;;279 clk_freq = (CPU_INT32U)(pll_clk_feq / clk_div); /* Compute the ARM Core clock frequency */
0000c0 e1a01008 MOV r1,r8
0000c4 e1a00007 MOV r0,r7
0000c8 ebfffffe BL __aeabi_uidivmod
0000cc e1a09000 MOV r9,r0
;;;280
;;;281 return (clk_freq);
0000d0 e1a00009 MOV r0,r9
0000d4 e8bd47f0 POP {r4-r10,lr}
;;;282 }
0000d8 e12fff1e BX lr
ENDP
BSP_CPU_PclkFreq PROC
;;;298 CPU_INT32U BSP_CPU_PclkFreq (CPU_INT08U pclk)
;;;299 {
0000dc e92d4070 PUSH {r4-r6,lr}
0000e0 e1a04000 MOV r4,r0
;;;300 CPU_INT32U clk_freq;
;;;301 CPU_INT32U selection;
;;;302
;;;303
;;;304 clk_freq = BSP_CPU_ClkFreq();
0000e4 ebfffffe BL BSP_CPU_ClkFreq
0000e8 e1a06000 MOV r6,r0
;;;305
;;;306 switch (pclk) {
0000ec e354001e CMP r4,#0x1e
0000f0 308ff104 ADDCC pc,pc,r4,LSL #2
0000f4 ea000061 B |L1.640|
0000f8 ea00001c B |L1.368|
0000fc ea00001d B |L1.376|
000100 ea00001d B |L1.380|
000104 ea00001d B |L1.384|
000108 ea00001d B |L1.388|
00010c ea00001d B |L1.392|
000110 ea00001d B |L1.396|
000114 ea00001d B |L1.400|
000118 ea00001d B |L1.404|
00011c ea00001d B |L1.408|
000120 ea00001d B |L1.412|
000124 ea00001d B |L1.416|
000128 ea00001d B |L1.420|
00012c ea00001d B |L1.424|
000130 ea00001d B |L1.428|
000134 ea00001d B |L1.432|
000138 ea000030 B |L1.512|
00013c ea000031 B |L1.520|
000140 ea000031 B |L1.524|
000144 ea000031 B |L1.528|
000148 ea00004c B |L1.640|
00014c ea000030 B |L1.532|
000150 ea000030 B |L1.536|
000154 ea000030 B |L1.540|
000158 ea000030 B |L1.544|
00015c ea000030 B |L1.548|
000160 ea000030 B |L1.552|
000164 ea000030 B |L1.556|
000168 ea000044 B |L1.640|
00016c ea00002f B |L1.560|
|L1.368|
;;;307 case PCLK_WDT:
000170 e1a00000 MOV r0,r0
;;;308 case PCLK_TIMER0:
000174 e1a00000 MOV r0,r0
|L1.376|
;;;309 case PCLK_TIMER1:
000178 e1a00000 MOV r0,r0
|L1.380|
;;;310 case PCLK_UART0:
00017c e1a00000 MOV r0,r0
|L1.384|
;;;311 case PCLK_UART1:
000180 e1a00000 MOV r0,r0
|L1.388|
;;;312 case PCLK_PWM0:
000184 e1a00000 MOV r0,r0
|L1.392|
;;;313 case PCLK_PWM1:
000188 e1a00000 MOV r0,r0
|L1.396|
;;;314 case PCLK_I2C0:
00018c e1a00000 MOV r0,r0
|L1.400|
;;;315 case PCLK_SPI:
000190 e1a00000 MOV r0,r0
|L1.404|
;;;316 case PCLK_RTC:
000194 e1a00000 MOV r0,r0
|L1.408|
;;;317 case PCLK_SSP1:
000198 e1a00000 MOV r0,r0
|L1.412|
;;;318 case PCLK_DAC:
00019c e1a00000 MOV r0,r0
|L1.416|
;;;319 case PCLK_ADC:
0001a0 e1a00000 MOV r0,r0
|L1.420|
;;;320 case PCLK_CAN1:
0001a4 e1a00000 MOV r0,r0
|L1.424|
;;;321 case PCLK_CAN2:
0001a8 e1a00000 MOV r0,r0
|L1.428|
;;;322 case PCLK_ACF:
0001ac e1a00000 MOV r0,r0
|L1.432|
;;;323 selection = ((PCLKSEL0 >> (pclk * 2)) & 0x03);
0001b0 e59f0cb8 LDR r0,|L1.3696|
0001b4 e59001a8 LDR r0,[r0,#0x1a8]
0001b8 e1a01084 LSL r1,r4,#1
0001bc e1a00130 LSR r0,r0,r1
0001c0 e2005003 AND r5,r0,#3
;;;324 if (selection == 0) {
0001c4 e3550000 CMP r5,#0
0001c8 1a000002 BNE |L1.472|
;;;325 return (clk_freq / 4);
0001cc e1a00126 LSR r0,r6,#2
|L1.464|
0001d0 e8bd4070 POP {r4-r6,lr}
;;;326 } else if (selection == 1) {
;;;327 return (clk_freq);
;;;328 } else if (selection == 2) {
;;;329 return (clk_freq / 2);
;;;330 } else {
;;;331 return (clk_freq / 8);
;;;332 }
;;;333
;;;334 case PCLK_BAT_RAM:
;;;335 case PCLK_GPIO:
;;;336 case PCLK_PCB:
;;;337 case PCLK_I2C1:
;;;338 case PCLK_SSP0:
;;;339 case PCLK_TIMER2:
;;;340 case PCLK_TIMER3:
;;;341 case PCLK_UART2:
;;;342 case PCLK_UART3:
;;;343 case PCLK_I2C2:
;;;344 case PCLK_MCI:
;;;345 case PCLK_SYSCON:
;;;346 selection = ((PCLKSEL1 >> ((pclk - 16) * 2)) & 0x03);
;;;347 if (selection == 0) {
;;;348 return (clk_freq / 4);
;;;349 } else if (selection == 1) {
;;;350 return (clk_freq);
;;;351 } else if (selection == 2) {
;;;352 return (clk_freq / 2);
;;;353 } else {
;;;354 return (clk_freq / 8);
;;;355 }
;;;356
;;;357 default:
;;;358 return (0);
;;;359 }
;;;360 }
0001d4 e12fff1e BX lr
|L1.472|
0001d8 e3550001 CMP r5,#1
0001dc 1a000001 BNE |L1.488|
0001e0 e1a00006 MOV r0,r6
0001e4 eafffff9 B |L1.464|
|L1.488|
0001e8 e3550002 CMP r5,#2
0001ec 1a000001 BNE |L1.504|
0001f0 e1a000a6 LSR r0,r6,#1
0001f4 eafffff5 B |L1.464|
|L1.504|
0001f8 e1a001a6 LSR r0,r6,#3
0001fc eafffff3 B |L1.464|
|L1.512|
000200 e1a00000 MOV r0,r0
000204 e1a00000 MOV r0,r0
|L1.520|
000208 e1a00000 MOV r0,r0
|L1.524|
00020c e1a00000 MOV r0,r0
|L1.528|
000210 e1a00000 MOV r0,r0
|L1.532|
000214 e1a00000 MOV r0,r0
|L1.536|
000218 e1a00000 MOV r0,r0
|L1.540|
00021c e1a00000 MOV r0,r0
|L1.544|
000220 e1a00000 MOV r0,r0
|L1.548|
000224 e1a00000 MOV r0,r0
|L1.552|
000228 e1a00000 MOV r0,r0
|L1.556|
00022c e1a00000 MOV r0,r0
|L1.560|
000230 e59f0c38 LDR r0,|L1.3696|
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