?? bsp.txt
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;;;1386
;;;1387 MAMCR = 0; /* Disable MAM functionality */
00090c e3a00000 MOV r0,#0
000910 e59f1558 LDR r1,|L1.3696|
000914 e5810000 STR r0,[r1,#0]
;;;1388
;;;1389 if (clk_freq < 20000000) { /* Compare current clock frequency with MAM modes */
000918 e59f0584 LDR r0,|L1.3748|
00091c e1540000 CMP r4,r0
000920 2a000002 BCS |L1.2352|
;;;1390 MAMTIM = 1; /* Set MAM fetch cycles to 1 processor clock in duration */
000924 e3a00001 MOV r0,#1
000928 e59f1540 LDR r1,|L1.3696|
00092c e5810004 STR r0,[r1,#4]
|L1.2352|
;;;1391 }
;;;1392
;;;1393 if (clk_freq < 40000000) {
000930 e59f0570 LDR r0,|L1.3752|
000934 e1540000 CMP r4,r0
000938 2a000002 BCS |L1.2376|
;;;1394 MAMTIM = 2; /* Set MAM fetch cycles to 2 processor clock in duration */
00093c e3a00002 MOV r0,#2
000940 e59f1528 LDR r1,|L1.3696|
000944 e5810004 STR r0,[r1,#4]
|L1.2376|
;;;1395 }
;;;1396
;;;1397 if (clk_freq >= 40000000) {
000948 e59f0558 LDR r0,|L1.3752|
00094c e1540000 CMP r4,r0
000950 3a000002 BCC |L1.2400|
;;;1398 MAMTIM = 3; /* Set MAM fetch cycles to 3 processor clock in duration */
000954 e3a00003 MOV r0,#3
000958 e59f1510 LDR r1,|L1.3696|
00095c e5810004 STR r0,[r1,#4]
|L1.2400|
;;;1399 }
;;;1400
;;;1401 MAMCR = 2; /* Enable full MAM functionality */
000960 e3a00002 MOV r0,#2
000964 e59f1504 LDR r1,|L1.3696|
000968 e5810000 STR r0,[r1,#0]
;;;1402 }
00096c e8bd4010 POP {r4,lr}
000970 e12fff1e BX lr
ENDP
PLL_Init PROC
;;;1295 static void PLL_Init (void)
;;;1296 {
000974 e92d41f0 PUSH {r4-r8,lr}
;;;1297 #if CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL /* Allocate storage for CPU status register */
;;;1298 CPU_SR cpu_sr = 0;
000978 e3a04000 MOV r4,#0
;;;1299 #endif
;;;1300
;;;1301 CPU_INT32U m;
;;;1302 CPU_INT32U n;
;;;1303 CPU_INT32U clk_div;
;;;1304 CPU_INT32U clk_div_usb;
;;;1305
;;;1306
;;;1307 m = 11; /* PLL Multiplier = 20, MSEL bits = 12 - 1 = 11 */
00097c e3a0500b MOV r5,#0xb
;;;1308 n = 0; /* PLL Divider = 1, NSEL bits = 1 - 1 = 0 */
000980 e3a06000 MOV r6,#0
;;;1309 clk_div = 5; /* Configure the ARM Core clock div to 6. CCLKSEL = 6 - 1 */
000984 e3a07005 MOV r7,#5
;;;1310 clk_div_usb = 5; /* Configure the USB clock divider to 6, USBSEL = 6 - 1 */
000988 e3a08005 MOV r8,#5
;;;1311
;;;1312 if ((PLLSTAT & (1 << 25)) > 0) { /* If the PLL is already running */
00098c e59f04dc LDR r0,|L1.3696|
000990 e5900088 LDR r0,[r0,#0x88]
000994 e3100402 TST r0,#0x2000000
000998 0a00000c BEQ |L1.2512|
;;;1313 CPU_CRITICAL_ENTER();
00099c ebfffffe BL CPU_SR_Save
0009a0 e1a04000 MOV r4,r0
;;;1314 PLLCON &= ~(1 << 1); /* Disconnect the PLL */
0009a4 e59f04c4 LDR r0,|L1.3696|
0009a8 e5900080 LDR r0,[r0,#0x80]
0009ac e3c00002 BIC r0,r0,#2
0009b0 e59f14b8 LDR r1,|L1.3696|
0009b4 e5810080 STR r0,[r1,#0x80]
;;;1315 PLLFEED = 0xAA; /* PLL register update sequence, 0xAA, 0x55 */
0009b8 e3a000aa MOV r0,#0xaa
0009bc e581008c STR r0,[r1,#0x8c]
;;;1316 PLLFEED = 0x55;
0009c0 e3a00055 MOV r0,#0x55
0009c4 e581008c STR r0,[r1,#0x8c]
;;;1317 CPU_CRITICAL_EXIT();
0009c8 e1a00004 MOV r0,r4
0009cc ebfffffe BL CPU_SR_Restore
|L1.2512|
;;;1318 }
;;;1319
;;;1320 CPU_CRITICAL_ENTER();
0009d0 ebfffffe BL CPU_SR_Save
0009d4 e1a04000 MOV r4,r0
;;;1321 PLLCON &= ~(1 << 0); /* Disable the PLL */
0009d8 e59f0490 LDR r0,|L1.3696|
0009dc e5900080 LDR r0,[r0,#0x80]
0009e0 e3c00001 BIC r0,r0,#1
0009e4 e59f1484 LDR r1,|L1.3696|
0009e8 e5810080 STR r0,[r1,#0x80]
;;;1322 PLLFEED = 0xAA; /* PLL register update sequence, 0xAA, 0x55 */
0009ec e3a000aa MOV r0,#0xaa
0009f0 e581008c STR r0,[r1,#0x8c]
;;;1323 PLLFEED = 0x55;
0009f4 e3a00055 MOV r0,#0x55
0009f8 e581008c STR r0,[r1,#0x8c]
;;;1324 CPU_CRITICAL_EXIT();
0009fc e1a00004 MOV r0,r4
000a00 ebfffffe BL CPU_SR_Restore
;;;1325
;;;1326 SCS &= ~(1 << 4); /* OSCRANGE = 0, Main OSC is between 1 and 20 Mhz */
000a04 e59f0464 LDR r0,|L1.3696|
000a08 e59001a0 LDR r0,[r0,#0x1a0]
000a0c e3c00010 BIC r0,r0,#0x10
000a10 e59f1458 LDR r1,|L1.3696|
000a14 e58101a0 STR r0,[r1,#0x1a0]
;;;1327 SCS |= (1 << 5); /* OSCEN = 1, Enable the main oscillator */
000a18 e1a00001 MOV r0,r1
000a1c e59001a0 LDR r0,[r0,#0x1a0]
000a20 e3800020 ORR r0,r0,#0x20
000a24 e58101a0 STR r0,[r1,#0x1a0]
;;;1328
;;;1329 while ((SCS & (1 << 6)) == 0) { /* Wait until OSCSTAT is set (Main OSC ready to be used) */
000a28 e1a00000 MOV r0,r0
|L1.2604|
000a2c e59f043c LDR r0,|L1.3696|
000a30 e59001a0 LDR r0,[r0,#0x1a0]
000a34 e3100040 TST r0,#0x40
000a38 0afffffb BEQ |L1.2604|
;;;1330 ;
;;;1331 }
;;;1332
;;;1333 CLKSRCSEL = (1 << 0); /* Select main OSC, 12MHz, as the PLL clock source */
000a3c e3a00001 MOV r0,#1
000a40 e59f1428 LDR r1,|L1.3696|
000a44 e581010c STR r0,[r1,#0x10c]
;;;1334
;;;1335 CPU_CRITICAL_ENTER();
000a48 ebfffffe BL CPU_SR_Save
000a4c e1a04000 MOV r4,r0
;;;1336 PLLCFG = (m << 0) | (n << 16); /* Configure the PLL multiplier and divider */
000a50 e1850806 ORR r0,r5,r6,LSL #16
000a54 e59f1414 LDR r1,|L1.3696|
000a58 e5810084 STR r0,[r1,#0x84]
;;;1337 PLLFEED = 0xAA; /* PLL register update sequence, 0xAA, 0x55 */
000a5c e3a000aa MOV r0,#0xaa
000a60 e581008c STR r0,[r1,#0x8c]
;;;1338 PLLFEED = 0x55;
000a64 e3a00055 MOV r0,#0x55
000a68 e581008c STR r0,[r1,#0x8c]
;;;1339 CPU_CRITICAL_EXIT();
000a6c e1a00004 MOV r0,r4
000a70 ebfffffe BL CPU_SR_Restore
;;;1340
;;;1341 CPU_CRITICAL_ENTER();
000a74 ebfffffe BL CPU_SR_Save
000a78 e1a04000 MOV r4,r0
;;;1342 PLLCON |= (1 << 0); /* Enable the PLL */
000a7c e59f03ec LDR r0,|L1.3696|
000a80 e5900080 LDR r0,[r0,#0x80]
000a84 e3800001 ORR r0,r0,#1
000a88 e59f13e0 LDR r1,|L1.3696|
000a8c e5810080 STR r0,[r1,#0x80]
;;;1343 PLLFEED = 0xAA; /* PLL register update sequence, 0xAA, 0x55 */
000a90 e3a000aa MOV r0,#0xaa
000a94 e581008c STR r0,[r1,#0x8c]
;;;1344 PLLFEED = 0x55;
000a98 e3a00055 MOV r0,#0x55
000a9c e581008c STR r0,[r1,#0x8c]
;;;1345 CPU_CRITICAL_EXIT();
000aa0 e1a00004 MOV r0,r4
000aa4 ebfffffe BL CPU_SR_Restore
;;;1346
;;;1347 CCLKCFG = clk_div; /* Configure the ARM Core Processor clock divider */
000aa8 e59f03c0 LDR r0,|L1.3696|
000aac e5807104 STR r7,[r0,#0x104]
;;;1348 USBCLKCFG = clk_div_usb; /* Configure the USB clock divider */
000ab0 e5808108 STR r8,[r0,#0x108]
;;;1349
;;;1350 while ((PLLSTAT & (1 << 26)) == 0) { /* Wait for PLOCK to become set */
000ab4 e1a00000 MOV r0,r0
|L1.2744|
000ab8 e59f03b0 LDR r0,|L1.3696|
000abc e5900088 LDR r0,[r0,#0x88]
000ac0 e3100301 TST r0,#0x4000000
000ac4 0afffffb BEQ |L1.2744|
;;;1351 ;
;;;1352 }
;;;1353
;;;1354 PCLKSEL0 = 0xAAAAAAAA; /* Set peripheral clocks to be half of main clock */
000ac8 e59f03dc LDR r0,|L1.3756|
000acc e59f139c LDR r1,|L1.3696|
000ad0 e58101a8 STR r0,[r1,#0x1a8]
;;;1355 PCLKSEL1 = 0x22AAA8AA;
000ad4 e59f03d4 LDR r0,|L1.3760|
000ad8 e58101ac STR r0,[r1,#0x1ac]
;;;1356
;;;1357 CPU_CRITICAL_ENTER();
000adc ebfffffe BL CPU_SR_Save
000ae0 e1a04000 MOV r4,r0
;;;1358 PLLCON |= (1 << 1); /* Connect the PLL. The PLL is now the active clock source */
000ae4 e59f0384 LDR r0,|L1.3696|
000ae8 e5900080 LDR r0,[r0,#0x80]
000aec e3800002 ORR r0,r0,#2
000af0 e59f1378 LDR r1,|L1.3696|
000af4 e5810080 STR r0,[r1,#0x80]
;;;1359 PLLFEED = 0xAA; /* PLL register update sequence, 0xAA, 0x55 */
000af8 e3a000aa MOV r0,#0xaa
000afc e581008c STR r0,[r1,#0x8c]
;;;1360 PLLFEED = 0x55;
000b00 e3a00055 MOV r0,#0x55
000b04 e581008c STR r0,[r1,#0x8c]
;;;1361 CPU_CRITICAL_EXIT();
000b08 e1a00004 MOV r0,r4
000b0c ebfffffe BL CPU_SR_Restore
;;;1362
;;;1363 while ((PLLSTAT & (1 << 25)) == 0) { /* Wait PLLC, the PLL connect status bit to become set */
000b10 e1a00000 MOV r0,r0
|L1.2836|
000b14 e59f0354 LDR r0,|L1.3696|
000b18 e5900088 LDR r0,[r0,#0x88]
000b1c e3100402 TST r0,#0x2000000
000b20 0afffffb BEQ |L1.2836|
;;;1364 ;
;;;1365 }
;;;1366 }
000b24 e8bd41f0 POP {r4-r8,lr}
000b28 e12fff1e BX lr
ENDP
BSP_Init PROC
;;;215 void BSP_Init (void)
;;;216 {
000b2c e92d4010 PUSH {r4,lr}
;;;217 PLL_Init(); /* Initialize the PLL */
000b30 ebfffffe BL PLL_Init
;;;218 MAM_Init(); /* Initialize the Memory Acceleration Module */
000b34 ebfffffe BL MAM_Init
;;;219 GPIO_Init(); /* Initialize the board's I/Os */
000b38 ebfffffe BL GPIO_Init
;;;220 ADC_Init(); /* Initialize the board's ADCs */
000b3c ebfffffe BL ADC_Init
;;;221 VIC_Init(); /* Initialize the Vectored Interrupt Controller */
000b40 ebfffffe BL VIC_Init
;;;222 I2C_Init(); /* Initialize the I2C */
000b44 ebfffffe BL I2C_Init
;;;223
;;;224 Tmr_TickInit(); /* Initialize the uC/OS-II tick interrupt */
000b48 ebfffffe BL Tmr_TickInit
;;;225 }
000b4c e8bd4010 POP {r4,lr}
000b50 e12fff1e BX lr
ENDP
BSP_IntDisAll PROC
;;;375 {
;;;376 VICIntEnClear = 0xFFFFFFFFL; /* Disable ALL interrupts */
000b54 e3e00000 MVN r0,#0
000b58 e3a01000 MOV r1,#0
000b5c e5010fec STR r0,[r1,#-0xfec]
;;;377 }
000b60 e12fff1e BX lr
ENDP
OS_CPU_ExceptHndlr PROC
;;;399 void OS_CPU_ExceptHndlr (CPU_DATA ID)
;;;400 {
000b64 e92d4070 PUSH {r4-r6,lr}
000b68 e1a05000 MOV r5,r0
;;;401 BSP_FNCT_PTR pfnct;
;;;402
;;;403 /* If this exception is either an IRQ or FIQ */
;;;404 if ((ID == OS_CPU_ARM_EXCEPT_IRQ) || (ID == OS_CPU_ARM_EXCEPT_FIQ)) {
000b6c e3550006 CMP r5,#6
000b70 0a000001 BEQ |L1.2940|
000b74 e3550007 CMP r5,#7
000b78 1a000008 BNE |L1.2976|
|L1.2940|
;;;405 pfnct = (BSP_FNCT_PTR)VICAddress; /* Read the interrupt vector from the VIC */
000b7c e3a00000 MOV r0,#0
000b80 e5104100 LDR r4,[r0,#-0x100]
;;;406 if (pfnct != (BSP_FNCT_PTR)0) { /* Make sure we don't have a NULL pointer */
000b84 e3540000 CMP r4,#0
000b88 0a000004 BEQ |L1.2976|
;;;407 (*pfn?? 快捷鍵說明
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