?? serial_test.vhd
字號(hào):
--
-- 本模塊的功能是驗(yàn)證實(shí)現(xiàn)和PC機(jī)進(jìn)行基本的串口通信的功能。需要在
--PC機(jī)上安裝一個(gè)串口調(diào)試工具來驗(yàn)證程序的功能。
-- 程序?qū)崿F(xiàn)了一個(gè)收發(fā)一幀10個(gè)bit（即無奇偶校驗(yàn)位）的串口控
--制器，10個(gè)bit是1位起始位，8個(gè)數(shù)據(jù)位，1個(gè)結(jié)束
--位。串口的波特律由程序中定義的div_par參數(shù)決定，更改該參數(shù)可以實(shí)
--現(xiàn)相應(yīng)的波特率。程序當(dāng)前設(shè)定的div_par 的值是0x104，對應(yīng)的波特率是
--9600。用一個(gè)8倍波特率的時(shí)鐘將發(fā)送或接受每一位bit的周期時(shí)間
--劃分為8個(gè)時(shí)隙以使通信同步.
--程序的工作過程是：串口處于全雙工工作狀態(tài)，按動(dòng)SW0，CPLD向PC發(fā)送“welcome"
--字符串（串口調(diào)試工具設(shè)成按ASCII碼接受方式）；PC可隨時(shí)向CPLD發(fā)送0-F的十六進(jìn)制
--數(shù)據(jù)，CPLD接受后顯示在7段數(shù)碼管上。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY serial_test IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
rxd : IN std_logic; --串行數(shù)據(jù)接收端
txd : OUT std_logic; --串行數(shù)據(jù)發(fā)送端
led : out std_logic_vector(7 downto 0)
);
END serial_test;
ARCHITECTURE arch OF serial_test IS
--//////////////////inner reg////////////////////
SIGNAL div_reg : std_logic_vector(15 DOWNTO 0);--分頻計(jì)數(shù)器，分頻值由波特率決定。分頻后得到頻率8倍波特率的時(shí)鐘
SIGNAL div8_tras_reg : std_logic_vector(2 DOWNTO 0);--該寄存器的計(jì)數(shù)值對應(yīng)發(fā)送時(shí)當(dāng)前位于的時(shí)隙數(shù)
SIGNAL div8_rec_reg : std_logic_vector(2 DOWNTO 0); --寄存器的計(jì)數(shù)值對應(yīng)接收時(shí)當(dāng)前位于的時(shí)隙數(shù)
SIGNAL state_tras : std_logic_vector(3 DOWNTO 0); -- 發(fā)送狀態(tài)寄存器
SIGNAL state_rec : std_logic_vector(3 DOWNTO 0); -- 接受狀態(tài)寄存器
SIGNAL clkbaud_tras : std_logic; --以波特率為頻率的發(fā)送使能信號(hào)
SIGNAL clkbaud_rec : std_logic; --以波特率為頻率的接受使能信號(hào)
SIGNAL clkbaud8x : std_logic; --以8倍波特率為頻率的時(shí)鐘，它的作用是將發(fā)送或接受一個(gè)bit的時(shí)鐘周期分為8個(gè)時(shí)隙
SIGNAL recstart : std_logic; -- 開始發(fā)送標(biāo)志
SIGNAL recstart_tmp : std_logic; --開始接受標(biāo)志
SIGNAL trasstart : std_logic;
SIGNAL rxd_reg1 : std_logic; --接收寄存器1
SIGNAL rxd_reg2 : std_logic; --接收寄存器2，因?yàn)榻邮諗?shù)據(jù)為異步信號(hào)，故用兩級緩存
SIGNAL txd_reg : std_logic; --發(fā)送寄存器
SIGNAL rxd_buf : std_logic_vector(7 DOWNTO 0);--接受數(shù)據(jù)緩存
SIGNAL txd_buf : std_logic_vector(7 DOWNTO 0);--發(fā)送數(shù)據(jù)緩存
SIGNAL send_state : std_logic_vector(2 DOWNTO 0);--每次按鍵給PC發(fā)送"Welcome"字符串，這是發(fā)送狀態(tài)寄存器
SIGNAL key_entry2 : std_logic; --確定有鍵按下標(biāo)志
--//////////////////////////////////////////////
CONSTANT div_par : std_logic_vector(15 DOWNTO 0) := "0000000000011011"; --"0000000101000101";
--分頻參數(shù)，其值由對應(yīng)的波特率計(jì)算而得，按此參數(shù)分頻的時(shí)鐘頻率是波倍特率的8倍，此處值對應(yīng)57600的波特率，即分頻出的時(shí)鐘頻率是115200*8
SIGNAL txd_xhdl3 : std_logic;
BEGIN
txd <= txd_xhdl3;
txd_xhdl3 <= txd_reg ;
led<=rxd_buf;
PROCESS(clk,rst)
BEGIN
IF (NOT rst = '1') THEN
div_reg <= "0000000000000000";
ELSIF(clk'EVENT AND clk='1')THEN
IF (div_reg = div_par - "0000000000000001") THEN
div_reg <= "0000000000000000";
ELSE
div_reg <= div_reg + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS(clk,rst) --分頻得到8倍波特率的時(shí)鐘
BEGIN
IF (NOT rst = '1') THEN
clkbaud8x <= '0';
ELSIF(clk'EVENT AND clk='1')THEN
IF (div_reg = div_par - "0000000000000001") THEN
clkbaud8x <= NOT clkbaud8x;
END IF;
END IF;
END PROCESS;
PROCESS(clkbaud8x,rst)
BEGIN
IF (NOT rst = '1') THEN
div8_rec_reg <= "000";
ELSE IF(clkbaud8x'EVENT AND clkbaud8x = '1') THEN
IF (recstart = '1') THEN --接收開始標(biāo)志
div8_rec_reg <= div8_rec_reg + "001";--接收開始后，時(shí)隙數(shù)在8倍波特率的時(shí)鐘下加1循環(huán)
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(clkbaud8x,rst)
BEGIN
IF (NOT rst = '1') THEN
div8_tras_reg <= "000";
ELSE IF(clkbaud8x'EVENT AND clkbaud8x = '1') THEN
IF (trasstart = '1') THEN
div8_tras_reg <= div8_tras_reg + "001";--發(fā)送開始后，時(shí)隙數(shù)在8倍波特率的時(shí)鐘下加1循環(huán)
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(div8_rec_reg)
BEGIN
IF (div8_rec_reg = "111") THEN
clkbaud_rec <= '1'; ---在第7個(gè)時(shí)隙，接收使能信號(hào)有效，將數(shù)據(jù)打入
ELSE
clkbaud_rec <= '0';
END IF;
END PROCESS;
PROCESS(div8_tras_reg)
BEGIN
IF (div8_tras_reg = "111") THEN
clkbaud_tras <= '1'; --在第7個(gè)時(shí)隙，發(fā)送使能信號(hào)有效，將數(shù)據(jù)發(fā)出
ELSE
clkbaud_tras <= '0';
END IF;
END PROCESS;
PROCESS(clkbaud8x,rst)
BEGIN
IF (NOT rst = '1') THEN
txd_reg <= '1';
trasstart <= '0';
txd_buf <= "00000000";
state_tras <= "0000";
send_state <= "000";
key_entry2 <= '1';
txd_buf <= "01110111"; --"w"
ELSE IF(clkbaud8x'EVENT AND clkbaud8x = '1') THEN
CASE state_tras IS
WHEN "0000" => --發(fā)送起始位
IF ((NOT trasstart='1') AND (send_state < "111") ) THEN
trasstart <= '1';
ELSE
IF (send_state < "111") THEN
IF (clkbaud_tras = '1') THEN
txd_reg <= '0';
state_tras <= state_tras + "0001";
END IF;
ELSE
key_entry2 <= '0';
state_tras <= "0000";
END IF;
END IF;
WHEN "0001" => --發(fā)送第1位
IF (clkbaud_tras = '1') THEN
txd_reg <= txd_buf(0);
txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);
state_tras <= state_tras + "0001";
END IF;
WHEN "0010" => --發(fā)送第2位
IF (clkbaud_tras = '1') THEN
txd_reg <= txd_buf(0);
txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);
state_tras <= state_tras + "0001";
END IF;
WHEN "0011" => --發(fā)送第3位
IF (clkbaud_tras = '1') THEN
txd_reg <= txd_buf(0);
txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);
state_tras <= state_tras + "0001";
END IF;
WHEN "0100" => --發(fā)送第4位
IF (clkbaud_tras = '1') THEN
txd_reg <= txd_buf(0);
txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);
state_tras <= state_tras + "0001";
END IF;
WHEN "0101" => --發(fā)送第5位
IF (clkbaud_tras = '1') THEN
txd_reg <= txd_buf(0);
txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);
state_tras <= state_tras + "0001";
END IF;
WHEN "0110" => --發(fā)送第6位
IF (clkbaud_tras = '1') THEN
txd_reg <= txd_buf(0);
txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);
state_tras <= state_tras + "0001";
END IF;
WHEN "0111" => --發(fā)送第7位
IF (clkbaud_tras = '1') THEN
txd_reg <= txd_buf(0);
txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);
state_tras <= state_tras + "0001";
END IF;
WHEN "1000" => --發(fā)送第8位
IF (clkbaud_tras = '1') THEN
txd_reg <= txd_buf(0);
txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);
state_tras <= state_tras + "0001";
END IF;
WHEN "1001" => --發(fā)送停止位
IF (clkbaud_tras = '1') THEN
txd_reg <= '1';
txd_buf <= "01010101";
state_tras <= state_tras + "0001";
END IF;
WHEN "1111" =>
IF (clkbaud_tras = '1') THEN
state_tras <= state_tras + "0001";
send_state <= send_state + "001";
trasstart <= '0';
CASE send_state IS
WHEN "000" =>
txd_buf <= "01100101"; --"e"
WHEN "001" =>
txd_buf <= "01101100"; --"l"
WHEN "010" =>
txd_buf <= "01100011"; --"c"
WHEN "011" =>
txd_buf <= "01101111"; --"o"
WHEN "100" =>
txd_buf <= "01101101"; --"m"
WHEN "101" =>
txd_buf <= "01100101";-- "e"
WHEN OTHERS =>
txd_buf <= "00000000";
END CASE;
END IF;
WHEN OTHERS =>
IF (clkbaud_tras = '1') THEN
state_tras <= state_tras + "0001";
trasstart <= '1';
END IF;
END CASE;
END IF;
END IF;
END PROCESS;
PROCESS(clkbaud8x,rst) --接受PC機(jī)的數(shù)據(jù)
BEGIN
IF (NOT rst = '1') THEN
rxd_reg1 <= '0';
rxd_reg2 <= '0';
rxd_buf <= "00000000";
state_rec <= "0000";
recstart <= '0';
recstart_tmp <= '0';
ELSE IF(clkbaud8x'EVENT AND clkbaud8x = '1') THEN
rxd_reg1 <= rxd;
rxd_reg2 <= rxd_reg1;
IF (state_rec = "0000") THEN
IF (recstart_tmp = '1') THEN
recstart <= '1';
recstart_tmp <= '0';
state_rec <= state_rec + "0001";
ELSE
IF ((NOT rxd_reg1 AND rxd_reg2) = '1') THEN --檢測到起始位的下降沿，進(jìn)入接受狀態(tài)
recstart_tmp <= '1';
END IF;
END IF;
ELSE
IF (state_rec >= "0001" AND state_rec<="1000") THEN
IF (clkbaud_rec = '1') THEN
rxd_buf(7) <= rxd_reg2;
rxd_buf(6 DOWNTO 0) <= rxd_buf(7 DOWNTO 1);
state_rec <= state_rec + "0001";
END IF;
ELSE
IF (state_rec = "1001") THEN
IF (clkbaud_rec = '1') THEN
state_rec <= "0000";
recstart <= '0';
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END arch;
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