/* 
 *  ======== evmdm642_mcbsp.h ======== 
 * 
 *  MCBSP interface on the DM642 EVM 
 */ 
#define  McBSP0_SPCR         *(unsigned int* 0x018C0008          
#define  McBSP0_RCR          *(unsigned int*)0x018C000C
#define  McBSP0_XCR          *(unsigned int*)0x01840010
#define  McBSP0_SRGR         *(unsigned int*)0x018C0014

//#define  McBSP0_DRR          *(unsigned int*)0x018c0000
#define  McBSP0_DRR          *(unsigned int*)0x30000000  

#define  McBSP0_MCR          *(unsigned int*)0x018C0018  
#define  McBSP0_PCR          *(unsigned int*)0x018C0024 


#define  McBSP1_SPCR         *(unsigned int*)0x01900008          
#define  McBSP1_RCR          *(unsigned int*)0x0190000C 
#define  McBSP1_XCR          *(unsigned int*)0x01900010
#define  McBSP1_SRGR         *(unsigned int*)0x01900014

//#define  McBSP1_DXR          *(unsigned int*)0x01900004
#define  McBSP1_DXR          *(unsigned int*)0x34000000
  
#define  McBSP1_MCR          *(unsigned int*)0x01900018  
#define  McBSP1_PCR          *(unsigned int*)0x01900024 


MCBSP_Config Mcbsp0 = {
  MCBSP_SPCR_RMK(
    MCBSP_SPCR_FREE_YES,
    MCBSP_SPCR_SOFT_YES,
    MCBSP_SPCR_FRST_NO,
    MCBSP_SPCR_GRST_NO,
    MCBSP_SPCR_XINTM_XRDY,
    MCBSP_SPCR_XSYNCERR_NO,
    MCBSP_SPCR_XRST_NO,
    MCBSP_SPCR_DLB_ON,
    MCBSP_SPCR_RJUST_RZF,
    MCBSP_SPCR_CLKSTP_DISABLE,
    MCBSP_SPCR_DXENA_OFF,
    MCBSP_SPCR_RINTM_RRDY,
    MCBSP_SPCR_RSYNCERR_NO,
    MCBSP_SPCR_RRST_NO
  ),
  MCBSP_RCR_RMK(
    MCBSP_RCR_RPHASE_SINGLE,
    MCBSP_RCR_RFRLEN2_OF(0),
    MCBSP_RCR_RWDLEN2_8BIT,
    MCBSP_RCR_RCOMPAND_MSB,
    MCBSP_RCR_RFIG_YES,
    MCBSP_RCR_RDATDLY_0BIT,
    MCBSP_RCR_RFRLEN1_OF(0), 
    MCBSP_RCR_RWDLEN1_32BIT,
    MCBSP_RCR_RWDREVRS_DISABLE
  ),
  MCBSP_XCR_RMK(
    MCBSP_XCR_XPHASE_SINGLE,
    MCBSP_XCR_XFRLEN2_OF(0),
    MCBSP_XCR_XWDLEN2_8BIT,
    MCBSP_XCR_XCOMPAND_MSB,
    MCBSP_XCR_XFIG_YES,
    MCBSP_XCR_XDATDLY_0BIT,
    MCBSP_XCR_XFRLEN1_OF(0), 
    MCBSP_XCR_XWDLEN1_32BIT,
    MCBSP_XCR_XWDREVRS_DISABLE
  ),
  MCBSP_SRGR_RMK(
    MCBSP_SRGR_GSYNC_FREE,
    MCBSP_SRGR_CLKSP_RISING,
    MCBSP_SRGR_CLKSM_INTERNAL,
    MCBSP_SRGR_FSGM_DXR2XSR,
    MCBSP_SRGR_FPER_OF(63),
    MCBSP_SRGR_FWID_OF(31),
    MCBSP_SRGR_CLKGDV_OF(15)
  ),
  MCBSP_MCR_DEFAULT,
  MCBSP_RCERE0_DEFAULT,
  MCBSP_RCERE1_DEFAULT,
  MCBSP_RCERE2_DEFAULT,
  MCBSP_RCERE3_DEFAULT,
  MCBSP_XCERE0_DEFAULT,
  MCBSP_XCERE1_DEFAULT,
  MCBSP_XCERE2_DEFAULT,
  MCBSP_XCERE3_DEFAULT,
  MCBSP_PCR_RMK(
    MCBSP_PCR_XIOEN_SP,
    MCBSP_PCR_RIOEN_SP,
    MCBSP_PCR_FSXM_INTERNAL,
    MCBSP_PCR_FSRM_EXTERNAL,
    MCBSP_PCR_CLKXM_OUTPUT,
    MCBSP_PCR_CLKRM_INPUT,
    MCBSP_PCR_CLKSSTAT_0,
    MCBSP_PCR_DXSTAT_0,
    MCBSP_PCR_DXSTAT_0,
    MCBSP_PCR_FSRP_ACTIVEHIGH,
    MCBSP_PCR_CLKXP_RISING,
    MCBSP_PCR_CLKRP_FALLING
  )
}; 


MCBSP_Config Mcbsp1 = {
  MCBSP_SPCR_RMK(
    MCBSP_SPCR_FREE_YES,
    MCBSP_SPCR_SOFT_YES,
    MCBSP_SPCR_FRST_NO,
    MCBSP_SPCR_GRST_NO,
    MCBSP_SPCR_XINTM_XRDY,
    MCBSP_SPCR_XSYNCERR_NO,
    MCBSP_SPCR_XRST_NO,
    MCBSP_SPCR_DLB_ON,
    MCBSP_SPCR_RJUST_RZF,
    MCBSP_SPCR_CLKSTP_DISABLE,
    MCBSP_SPCR_DXENA_OFF,
    MCBSP_SPCR_RINTM_RRDY,
    MCBSP_SPCR_RSYNCERR_NO,
    MCBSP_SPCR_RRST_NO
  ),
  MCBSP_RCR_RMK(
    MCBSP_RCR_RPHASE_SINGLE,
    MCBSP_RCR_RFRLEN2_OF(0),
    MCBSP_RCR_RWDLEN2_8BIT,
    MCBSP_RCR_RCOMPAND_MSB,
    MCBSP_RCR_RFIG_YES,
    MCBSP_RCR_RDATDLY_0BIT,
    MCBSP_RCR_RFRLEN1_OF(0), 
    MCBSP_RCR_RWDLEN1_32BIT,
    MCBSP_RCR_RWDREVRS_DISABLE
  ),
  MCBSP_XCR_RMK(
    MCBSP_XCR_XPHASE_SINGLE,
    MCBSP_XCR_XFRLEN2_OF(0),
    MCBSP_XCR_XWDLEN2_8BIT,
    MCBSP_XCR_XCOMPAND_MSB,
    MCBSP_XCR_XFIG_YES,
    MCBSP_XCR_XDATDLY_0BIT,
    MCBSP_XCR_XFRLEN1_OF(0), 
    MCBSP_XCR_XWDLEN1_32BIT,
    MCBSP_XCR_XWDREVRS_DISABLE
  ),
  MCBSP_SRGR_RMK(
    MCBSP_SRGR_GSYNC_FREE,
    MCBSP_SRGR_CLKSP_RISING,
    MCBSP_SRGR_CLKSM_INTERNAL,
    MCBSP_SRGR_FSGM_DXR2XSR,
    MCBSP_SRGR_FPER_OF(63),
    MCBSP_SRGR_FWID_OF(31),
    MCBSP_SRGR_CLKGDV_OF(15)
  ),
  MCBSP_MCR_DEFAULT,
  MCBSP_RCERE0_DEFAULT,
  MCBSP_RCERE1_DEFAULT,
  MCBSP_RCERE2_DEFAULT,
  MCBSP_RCERE3_DEFAULT,
  MCBSP_XCERE0_DEFAULT,
  MCBSP_XCERE1_DEFAULT,
  MCBSP_XCERE2_DEFAULT,
  MCBSP_XCERE3_DEFAULT,
  MCBSP_PCR_RMK(
    MCBSP_PCR_XIOEN_SP,
    MCBSP_PCR_RIOEN_SP,
    MCBSP_PCR_FSXM_INTERNAL,
    MCBSP_PCR_FSRM_EXTERNAL,
    MCBSP_PCR_CLKXM_OUTPUT,
    MCBSP_PCR_CLKRM_INPUT,
    MCBSP_PCR_CLKSSTAT_0,
    MCBSP_PCR_DXSTAT_0,
    MCBSP_PCR_DXSTAT_0,
    MCBSP_PCR_FSRP_ACTIVEHIGH,
    MCBSP_PCR_CLKXP_RISING,
    MCBSP_PCR_CLKRP_FALLING
  )
};