?? main.c.bak
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/*****************************************************************************
*
* Filename: main.c
*
* Description:
*
*
* Version:
*
*
* Date:
*
*
* Author:
*
*
*****************************************************************************/
/*****************************************************************************
*
* History:
*
*
*****************************************************************************/
#include <csl.h>
#include <csl_emifa.h>
#include <csl_i2c.h>
#include <csl_gpio.h>
#include <csl_cache.h>
#include <csl_mcbsp.h>
#include <stdio.h>
#include <math.h>
#include "evmdm642_mcbsp.h"
/* I2C handle */
I2C_Handle EVMDM642_I2C_hI2C;
/* GPIO handle */
GPIO_Handle EVMDM642_GPIO_hGPIO;
static GPIO_Config HS_Gpio_W = {
0x00000011, /* gpgc */
0x0000ff00, /* gpen */
0x0000ff00, /* gdir */
0x00000050, /* gpval */
0x00000000, /* gphm */
0x00000000, /* gplm */
0x00000030 /* gppol */
};
static GPIO_Config HS_Gpio_R = {
0x00000011, /* gpgc */
0x0000ff00, /* gpen */
0x00000000, /* gdir */
0x00000050, /* gpval */
0x00000000, /* gphm */
0x00000000, /* gplm */
0x00000030 /* gppol */
};
void DM642_wait(Uint32 delay)
{
volatile Uint32 i, n;
n = 0;
for (i = 0; i < delay; i++)
{
n = n + 1;
}
}
void mcbsp0_write(int out_data) //串口0寫
{
McBSP1_DXR = out_data;
}
int mcbsp0_read() //串口0讀
{
int temp;
temp = McBSP0_DRR;
return temp;
}
/* Initialize the board APIs */
void DM642_VIDEO_EVM_init()
{
volatile Uint32 test;
EMIFA_Config emifaCfg0 = {
EMIFA_FMKS(GBLCTL, EK2RATE, HALFCLK) |
EMIFA_FMKS(GBLCTL, EK2HZ, CLK) |
EMIFA_FMKS(GBLCTL, EK2EN, ENABLE) |
EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS) |
EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE) |
EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ) |
EMIFA_FMKS(GBLCTL, EK1EN, ENABLE) |
EMIFA_FMKS(GBLCTL, CLK4EN, ENABLE) |
EMIFA_FMKS(GBLCTL, CLK6EN, ENABLE),
EMIFA_FMKS(CECTL, WRSETUP, DEFAULT) |
EMIFA_FMKS(CECTL, WRSTRB, DEFAULT) |
EMIFA_FMKS(CECTL, WRHLD, DEFAULT) |
EMIFA_FMKS(CECTL, RDSETUP, DEFAULT) |
EMIFA_FMKS(CECTL, TA, DEFAULT) |
EMIFA_FMKS(CECTL, RDSTRB, DEFAULT) |
EMIFA_FMKS(CECTL, MTYPE, SDRAM64) |
EMIFA_FMKS(CECTL, RDHLD, DEFAULT),
EMIFA_FMKS(CECTL, WRSETUP, OF(7)) |
EMIFA_FMKS(CECTL, WRSTRB, OF(14)) |
EMIFA_FMKS(CECTL, WRHLD, OF(2)) |
EMIFA_FMKS(CECTL, RDSETUP, OF(2)) |
EMIFA_FMKS(CECTL, TA, OF(2)) |
EMIFA_FMKS(CECTL, RDSTRB, OF(14)) |
EMIFA_FMKS(CECTL, MTYPE, ASYNC16) |
EMIFA_FMKS(CECTL, RDHLD, OF(1)),
EMIFA_FMKS(CECTL, WRSETUP, OF(2)) |
EMIFA_FMKS(CECTL, WRSTRB, OF(10)) |
EMIFA_FMKS(CECTL, WRHLD, OF(2)) |
EMIFA_FMKS(CECTL, RDSETUP, OF(2)) |
EMIFA_FMKS(CECTL, TA, OF(2)) |
EMIFA_FMKS(CECTL, RDSTRB, OF(10)) |
EMIFA_FMKS(CECTL, MTYPE, ASYNC8) |
EMIFA_FMKS(CECTL, RDHLD, OF(2)),
EMIFA_FMKS(CECTL, WRSETUP, OF(2)) |
EMIFA_FMKS(CECTL, WRSTRB, OF(10)) |
EMIFA_FMKS(CECTL, WRHLD, OF(2)) |
EMIFA_FMKS(CECTL, RDSETUP, OF(2)) |
EMIFA_FMKS(CECTL, TA, OF(2)) |
EMIFA_FMKS(CECTL, RDSTRB, OF(10)) |
EMIFA_FMKS(CECTL, MTYPE, SYNC32) |
EMIFA_FMKS(CECTL, RDHLD, OF(2)),
EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS) |
EMIFA_FMKS(SDCTL, SDRSZ, 12ROW) |
EMIFA_FMKS(SDCTL, SDCSZ, 8COL) |
EMIFA_FMKS(SDCTL, RFEN, ENABLE) |
EMIFA_FMKS(SDCTL, INIT, YES) |
EMIFA_FMKS(SDCTL, TRCD, OF(1)) |
EMIFA_FMKS(SDCTL, TRP, OF(1)) |
EMIFA_FMKS(SDCTL, TRC, OF(5)) |
EMIFA_FMKS(SDCTL, SLFRFR, DISABLE),
EMIFA_FMKS(SDTIM, XRFR, OF(0)) |
EMIFA_FMKS(SDTIM, PERIOD, OF(2075)),
EMIFA_FMKS(SDEXT, WR2RD, OF(1)) |
EMIFA_FMKS(SDEXT, WR2DEAC, OF(3)) |
EMIFA_FMKS(SDEXT, WR2WR, OF(1)) |
EMIFA_FMKS(SDEXT, R2WDQM, OF(3)) |
EMIFA_FMKS(SDEXT, RD2WR, OF(2)) |
EMIFA_FMKS(SDEXT, RD2DEAC, OF(3)) |
EMIFA_FMKS(SDEXT, RD2RD, OF(1)) |
EMIFA_FMKS(SDEXT, THZP, OF(2)) |
EMIFA_FMKS(SDEXT, TWR, OF(2)) |
EMIFA_FMKS(SDEXT, TRRD, OF(0)) |
EMIFA_FMKS(SDEXT, TRAS, OF(6)) |
EMIFA_FMKS(SDEXT, TCL, OF(1)),
EMIFA_CESEC_DEFAULT,
EMIFA_CESEC_DEFAULT,
EMIFA_CESEC_DEFAULT,
EMIFA_FMKS(CESEC, SNCCLK, ECLKOUT2) |
EMIFA_FMKS(CESEC, RENEN, READ) |
EMIFA_FMKS(CESEC, CEEXT, ACTIVE) |
EMIFA_FMKS(CESEC, SYNCWL, 0CYCLE) |
EMIFA_FMKS(CESEC, SYNCRL, 3CYCLE)
};
I2C_Config i2cCfg = {
0x0000007f, /* I2COAR - Not used if master */
0x00000000, /* I2CIER - Disable interrupts, use polling */
0x0000001b, /* I2CCLKL - Low period for 100KHz operation */
0x0000001b, /* I2CCLKH - High period for 100KHz operation */
0x00000002, /* I2CCNT - Data words per transmission */
0x0000001a, /* I2CSAR - Slave address */
0x00004680, /* I2CMDR - Mode */
0x00000019 /* I2CPSC - Prescale 300MHz to 12MHz */
};
/* Initialize CSL */
CSL_init();
/* Unlock PERCFG through PCFGLOCK */
*((unsigned int *)0x01b3f018) = 0x10c0010c;
/* Enable VP0-VP2, I2C and McASP0 in PERCFG */
*((unsigned int *)0x01b3f000) = 0x79;
/* Read back PERCFG */
test = *((unsigned int *)0x01b3f000);
/* Wait at least 128 CPU cycles */
DM642_wait(128);
/* Initialize EMIFA */
EMIFA_config(&emifaCfg0);
/* Open I2C handle */
EVMDM642_I2C_hI2C = I2C_open(I2C_PORT0, I2C_OPEN_RESET);
/* Configure I2C controller */
I2C_config(EVMDM642_I2C_hI2C, &i2cCfg);
/* Take I2C out of reset */
I2C_outOfReset(EVMDM642_I2C_hI2C);
/* Open the GPIO handle */
EVMDM642_GPIO_hGPIO = GPIO_open(GPIO_DEV0, GPIO_OPEN_RESET);
/* Enable caching of SDRAM */
CACHE_enableCaching(CACHE_EMIFA_CE00);
CACHE_enableCaching(CACHE_EMIFA_CE01);
}
void mcbsp0_init() //配置McBSP0為SPI從設備
{
//復位串口的收發，禁用時間停止模式
McBSP0_SPCR = 0x00000000;
//Sleep(1000);
//配置SPCR PCR RCR XCR SRGR寄存器
McBSP0_RCR = 0x00040040; //16bit
McBSP0_XCR = 0x00040040; //16bit
//McBSP0_SRGR = 0x20000001;
McBSP0_PCR = 0x0000000C;
//啟動采樣率發生器
McBSP0_SPCR = 0x00400000;
//Sleep(1000);
//使能串口的收發，選擇時間停止模式
McBSP0_SPCR = 0x00C10001;
//Sleep(1000);
}
void mcbsp1_init() //配置McBSP0為SPI主設備
{
//復位串口的收發，禁用時間停止模式
McBSP1_SPCR = 0x00000000;
//Sleep(1000);
//配置SPCR PCR RCR XCR SRGR寄存器
McBSP1_RCR = 0x00010040;
McBSP1_XCR = 0x00010040;
McBSP1_SRGR = 0x200F010F;
McBSP1_PCR = 0x00000A7F;
//啟動采樣率發生器
McBSP1_SPCR = 0x00400000;
//Sleep(1000);
//使能串口的收發，選擇時間停止模式
McBSP1_SPCR = 0x00C11801;
//Sleep(1000);
}
void main()
{
MCBSP_Handle myhMcbsp0;
MCBSP_Handle myhMcbsp1;
int tmp8,tmp9,tmp10,tmp11,tmp12,tmp13,tmp14,tmp15, tmp,value,i = 0;
Int16 dataA, dataB;
Int16 outA, outB;
DM642_VIDEO_EVM_init();
myhMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET);//mcbsp1
//mcbsp0_init();
MCBSP_config(myhMcbsp0,&Mcbsp0);
MCBSP_enableSrgr(myhMcbsp0);//Enable the McBSP
MCBSP_enableFsync(myhMcbsp0);
MCBSP_enableRcv(myhMcbsp0);
myhMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);//mcbsp1
//mcbsp1_init();
MCBSP_config(myhMcbsp1,&Mcbsp1);
MCBSP_enableSrgr(myhMcbsp1);//Enable the McBSP
MCBSP_enableFsync(myhMcbsp1);
MCBSP_enableXmt(myhMcbsp1);
while(1)
{
GPIO_config(EVMDM642_GPIO_hGPIO, &HS_Gpio_W);
GPIO_pinWrite(EVMDM642_GPIO_hGPIO, GPIO_PIN8, i);
GPIO_pinWrite(EVMDM642_GPIO_hGPIO, GPIO_PIN9, i);
GPIO_pinWrite(EVMDM642_GPIO_hGPIO, GPIO_PIN10, i);
GPIO_pinWrite(EVMDM642_GPIO_hGPIO, GPIO_PIN11, i);
i = 1 - i;
GPIO_pinWrite(EVMDM642_GPIO_hGPIO, GPIO_PIN12, i);
GPIO_pinWrite(EVMDM642_GPIO_hGPIO, GPIO_PIN13, i);
GPIO_pinWrite(EVMDM642_GPIO_hGPIO, GPIO_PIN14, i);
GPIO_pinWrite(EVMDM642_GPIO_hGPIO, GPIO_PIN15, i);
GPIO_config(EVMDM642_GPIO_hGPIO, &HS_Gpio_R);
tmp8 = GPIO_pinRead(EVMDM642_GPIO_hGPIO, GPIO_PIN8);
//printf("GPIO_PIN08 value:%d\n",tmp8);
tmp9 = GPIO_pinRead(EVMDM642_GPIO_hGPIO, GPIO_PIN9);
//printf("GPIO_PIN09 value:%d\n",tmp9);
tmp10 = GPIO_pinRead(EVMDM642_GPIO_hGPIO, GPIO_PIN10);
//printf("GPIO_PIN10 value:%d\n",tmp10);
tmp11 = GPIO_pinRead(EVMDM642_GPIO_hGPIO, GPIO_PIN11);
//printf("GPIO_PIN11 value:%d\n",tmp11);
tmp12 = GPIO_pinRead(EVMDM642_GPIO_hGPIO, GPIO_PIN12);
//printf("GPIO_PIN12 value:%d\n",tmp12);
tmp13 = GPIO_pinRead(EVMDM642_GPIO_hGPIO, GPIO_PIN13);
//printf("GPIO_PIN13 value:%d\n",tmp13);
tmp14 = GPIO_pinRead(EVMDM642_GPIO_hGPIO, GPIO_PIN14);
//printf("GPIO_PIN14 value:%d\n",tmp14);
tmp15 = GPIO_pinRead(EVMDM642_GPIO_hGPIO, GPIO_PIN15);
//printf("GPIO_PIN15 value:%d\n",tmp15);
printf("GPIO15-GPIO8 value:%d%d%d%d%d%d%d%d\n",tmp15,tmp14,tmp13,tmp12,tmp11,tmp10,tmp9,tmp8);
dataA = 0x02aa;
dataB = 0x0155;
outA = 0xc000 & (dataA<<2);
outB = 0x4000 & (dataB<<2);
tmp = MCBSP_xrdy(myhMcbsp1);
if(tmp == 0)
MCBSP_write(myhMcbsp1,outA);
tmp = MCBSP_rrdy(myhMcbsp0);
if(tmp == 0)
{
value = MCBSP_read(myhMcbsp0);
printf("value:%d\n",value);
}
}
}
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