/*****************************************************************************
 *
 * Filename: main.c 
 *
 * Description:
 *      
 *
 * Version:
 *      
 *
 * Date: 
 *      
 *
 * Author:
 *      
 *
 *****************************************************************************/ 
/*****************************************************************************
 *
 * History:
 *     
 *
 *****************************************************************************/ 
#include <csl.h>
#include <csl_emifa.h>
#include <csl_i2c.h>
#include <csl_gpio.h>
#include <csl_cache.h>
#include <csl_mcbsp.h>
#include <stdio.h>
#include <math.h>
#include "iic.h"

unsigned int read_buffer[100];
int *p;

/* GPIO handle */
GPIO_Handle EVMDM642_GPIO_hGPIO;
/* I2C handle */
I2C_Handle EVMDM642_I2C_hI2C;

static GPIO_Config HS_Gpio_W = {
	0x00000011, /* gpgc */
	0x0000ff00, /* gpen */
	0x0000ff00, /* gdir */
	0x00000050, /* gpval */
	0x00000000, /* gphm */
	0x00000000, /* gplm */
	0x00000030  /* gppol */
};

static GPIO_Config HS_Gpio_R = {
	0x00000011, /* gpgc */
	0x0000ff00, /* gpen */
	0x00000000, /* gdir */
	0x00000050, /* gpval */
	0x00000000, /* gphm */
	0x00000000, /* gplm */
	0x00000030  /* gppol */
};

void DM642_wait(Uint32 delay)
{
    volatile Uint32 i, n;
    
    n = 0;
    for (i = 0; i < delay; i++)
    {
        n = n + 1;
    }
}
/* Initialize the board APIs */
void DM642_VIDEO_EVM_init()
{
    volatile Uint32 test;
    
    EMIFA_Config emifaCfg0 = {
        EMIFA_FMKS(GBLCTL, EK2RATE, HALFCLK)    |
        EMIFA_FMKS(GBLCTL, EK2HZ, CLK)          |
        EMIFA_FMKS(GBLCTL, EK2EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS)    |
        EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE)     |
        EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ)        |
        EMIFA_FMKS(GBLCTL, EK1EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, CLK4EN, ENABLE)      |
        EMIFA_FMKS(GBLCTL, CLK6EN, ENABLE),
        
        EMIFA_FMKS(CECTL, WRSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, WRSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, WRHLD, DEFAULT)      |
        EMIFA_FMKS(CECTL, RDSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, TA, DEFAULT)         |
        EMIFA_FMKS(CECTL, RDSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, MTYPE, SDRAM64)      |
        EMIFA_FMKS(CECTL, RDHLD, DEFAULT),
        
        EMIFA_FMKS(CECTL, WRSETUP, OF(7))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC16)       |
        EMIFA_FMKS(CECTL, RDHLD, OF(1)),
        
        EMIFA_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC8)      |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),

        EMIFA_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, SYNC32)       |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),
        
        EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS)       |
        EMIFA_FMKS(SDCTL, SDRSZ, 12ROW)        |
        EMIFA_FMKS(SDCTL, SDCSZ, 8COL)         |
        EMIFA_FMKS(SDCTL, RFEN, ENABLE)        |
        EMIFA_FMKS(SDCTL, INIT, YES)           |
        EMIFA_FMKS(SDCTL, TRCD, OF(1))         |
        EMIFA_FMKS(SDCTL, TRP, OF(1))          |
        EMIFA_FMKS(SDCTL, TRC, OF(5))          |
        EMIFA_FMKS(SDCTL, SLFRFR, DISABLE),
        
        EMIFA_FMKS(SDTIM, XRFR, OF(0))         |
        EMIFA_FMKS(SDTIM, PERIOD, OF(2075)),
        
        EMIFA_FMKS(SDEXT, WR2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, WR2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, WR2WR, OF(1))        |
        EMIFA_FMKS(SDEXT, R2WDQM, OF(3))       |
        EMIFA_FMKS(SDEXT, RD2WR, OF(2))        |
        EMIFA_FMKS(SDEXT, RD2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, RD2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, THZP, OF(2))         |
        EMIFA_FMKS(SDEXT, TWR, OF(2))          |
        EMIFA_FMKS(SDEXT, TRRD, OF(0))         |
        EMIFA_FMKS(SDEXT, TRAS, OF(6))         |
        EMIFA_FMKS(SDEXT, TCL, OF(1)),           
        
        EMIFA_CESEC_DEFAULT,

        EMIFA_CESEC_DEFAULT,

        EMIFA_CESEC_DEFAULT,

        EMIFA_FMKS(CESEC, SNCCLK, ECLKOUT2)    |
        EMIFA_FMKS(CESEC, RENEN, READ)         |
        EMIFA_FMKS(CESEC, CEEXT, ACTIVE)       |
        EMIFA_FMKS(CESEC, SYNCWL, 0CYCLE)      |
        EMIFA_FMKS(CESEC, SYNCRL, 3CYCLE)
    };

    I2C_Config i2cCfg = {
        0x0000007f, /* I2COAR -    Not used if master */
        0x00000000, /* I2CIER -    Disable interrupts, use polling */
        0x0000001b, /* I2CCLKL -   Low period for 100KHz operation */
        0x0000001b, /* I2CCLKH -   High period for 100KHz operation */
        0x00000002, /* I2CCNT -    Data words per transmission */
        0x0000001a, /* I2CSAR -    Slave address */
        0x00004680, /* I2CMDR -    Mode */
        0x00000019  /* I2CPSC -    Prescale 300MHz to 12MHz */
    };
        
    /* Initialize CSL */
    CSL_init();
    
    /* Unlock PERCFG through PCFGLOCK */
	*((unsigned int *)0x01b3f018) = 0x10c0010c;
    
    /* Enable VP0-VP2, I2C McBsp0,McBsp1 and McASP0  in PERCFG */
	*((unsigned int *)0x01b3f000) = 0x7f;
    
    /* Read back PERCFG */
	test = *((unsigned int *)0x01b3f000);


    
    /* Wait at least 128 CPU cycles */
    DM642_wait(128);

    /* Initialize EMIFA */
    EMIFA_config(&emifaCfg0);

    /* Open I2C handle */
    EVMDM642_I2C_hI2C = I2C_open(I2C_PORT0, I2C_OPEN_RESET);

    /* Configure I2C controller */
    I2C_config(EVMDM642_I2C_hI2C, &i2cCfg);

    /* Take I2C out of reset */        
    I2C_outOfReset(EVMDM642_I2C_hI2C);
    
    /* Open the GPIO handle */
    EVMDM642_GPIO_hGPIO = GPIO_open(GPIO_DEV0, GPIO_OPEN_RESET);

    /* Enable caching of SDRAM */
    CACHE_enableCaching(CACHE_EMIFA_CE00);
    CACHE_enableCaching(CACHE_EMIFA_CE01);
    
}



unsigned char data[10] = {0,1,2,3,4,5,6,7,8,9};             
void main()
{
	int i,j;
	DM642_VIDEO_EVM_init();
	GPIO_config(EVMDM642_GPIO_hGPIO, &HS_Gpio_W);
	GPIO_pinWrite(EVMDM642_GPIO_hGPIO, GPIO_PIN8, 0);
	DM642_wait(800);
	GPIO_pinWrite(EVMDM642_GPIO_hGPIO, GPIO_PIN8, 1);
	DM642_wait(800);
	while(1)
	{
		
		//IIC_write(EVMDM642_I2C_hI2C, 0xBA,0xf0,data,10);
		i = IIC_read16(EVMDM642_I2C_hI2C, (0xBA>>1),0x00);
		//i = IIC_read8(EVMDM642_I2C_hI2C, (0xBA>>1),0x0d);
		//j = IIC_read8(EVMDM642_I2C_hI2C, (0xBA>>1),0xf1);
   	    printf("read i:0x%x\n",i);
   	    //printf("read j:0x%x\n",j);
   	    
	}
}