r = Fitter-inserted logic cell


Device-Specific Information:                             f:\keshe\count100.rpt
count100

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                           Logic cells placed in LAB 'B'
        +----------------- LC23 count000
        | +--------------- LC26 count001
        | | +------------- LC17 count002
        | | | +----------- LC19 count003
        | | | | +--------- LC21 count010
        | | | | | +------- LC18 count011
        | | | | | | +----- LC24 count012
        | | | | | | | +--- LC27 count013
        | | | | | | | | +- LC22 co1
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC23 -> * * * * * * * * * | - * | <-- count000
LC26 -> * * * * * * * * * | - * | <-- count001
LC17 -> * - * * * * * * * | - * | <-- count002
LC19 -> * * * * * * * * * | - * | <-- count003
LC21 -> - - - - * * * * * | - * | <-- count010
LC18 -> - - - - * * * * * | - * | <-- count011
LC24 -> - - - - * - * * * | - * | <-- count012
LC27 -> - - - - * * * * * | - * | <-- count013
LC22 -> - - - - - - - - * | - * | <-- co1

Pin
43   -> - - - - - - - - - | - - | <-- clk
5    -> * * * * * * * * * | - * | <-- kn
4    -> * * * * * * * * - | - * | <-- rd


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                             f:\keshe\count100.rpt
count100

** EQUATIONS **

clk      : INPUT;
kn       : INPUT;
rd       : INPUT;

-- Node name is 'count000' = 'cnt00' 
-- Equation name is 'count000', location is LC023, type is output.
 count000 = DFFE( _EQ001 $ !kn, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ001 = !count000 & !count001 & !count002 &  kn
         # !count000 & !count003 &  kn
         # !count000 & !kn;

-- Node name is 'count001' = 'cnt01' 
-- Equation name is 'count001', location is LC026, type is output.
 count001 = TFFE( _EQ002, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ002 =  count000 & !count001 & !count003 &  kn
         #  count000 &  count001 &  kn
         #  count001 &  count003 &  kn;

-- Node name is 'count002' = 'cnt02' 
-- Equation name is 'count002', location is LC017, type is output.
 count002 = TFFE( _EQ003, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ003 =  count000 &  count001 & !count002 & !count003 &  kn
         #  count000 &  count001 &  count002 &  kn
         #  count002 &  count003 &  kn;

-- Node name is 'count003' = 'cnt03' 
-- Equation name is 'count003', location is LC019, type is output.
 count003 = TFFE(!_EQ004, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ004 = !count000 & !count001 & !count002 &  count003 &  _X001
         # !count003 &  _X001
         # !kn;
  _X001  = EXP( count000 &  count001 &  count002);

-- Node name is 'count010' = 'cnt10' 
-- Equation name is 'count010', location is LC021, type is output.
 count010 = TFFE(!_EQ005, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ005 = !count010 &  count013 &  _X002
         # !count000 & !count001 & !count002
         #  _X003;
  _X002  = EXP(!count011 & !count012);
  _X003  = EXP( count003 &  kn);

-- Node name is 'count011' = 'cnt11' 
-- Equation name is 'count011', location is LC018, type is output.
 count011 = TFFE( _EQ006, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ006 =  count003 &  count010 & !count011 & !count013 &  kn &  _X004
         #  count003 &  count010 &  count011 &  kn &  _X004
         #  count003 &  count011 &  count013 &  kn &  _X004;
  _X004  = EXP(!count000 & !count001 & !count002);

-- Node name is 'count012' = 'cnt12' 
-- Equation name is 'count012', location is LC024, type is output.
 count012 = TFFE( _EQ007, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ007 =  count003 &  count010 &  count011 & !count012 & !count013 &  kn & 
              _X004
         #  count003 &  count010 &  count011 &  count012 &  kn &  _X004
         #  count003 &  count012 &  count013 &  kn &  _X004;
  _X004  = EXP(!count000 & !count001 & !count002);

-- Node name is 'count013' = 'cnt13' 
-- Equation name is 'count013', location is LC027, type is output.
 count013 = TFFE(!_EQ008, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ008 = !count010 & !count011 & !count012 &  count013 &  _X005
         # !count000 & !count001 & !count002
         # !count013 &  _X005
         #  _X003;
  _X005  = EXP( count010 &  count011 &  count012);
  _X003  = EXP( count003 &  kn);

-- Node name is 'co1' = ':12' 
-- Equation name is 'co1', type is output 
 co1     = TFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 = !count000 & !count001 & !count002 &  count003 &  count010 & 
             !count011 & !count012 &  count013 & !co1 &  kn
         #  count000 &  count003 &  count013 &  co1 &  kn &  _X006
         #  count001 &  count003 &  count013 &  co1 &  kn &  _X006
         #  count002 &  count003 &  count013 &  co1 &  kn &  _X006;
  _X006  = EXP(!count010 & !count011 & !count012);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                      f:\keshe\count100.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,561K