?? usb_drv.lis
字號:
0000 ; System Status and Control Registers
0000 ;------------------------------------------------------
0000 ; Register bank 1.
0000 ;------------------------------------------------------
00E0 OSC_CR0: equ E0h ; System Oscillator Control Register 0 (RW)
0020 OSC_CR0_NO_BUZZ: equ 20h ; MASK: Bandgap always powered/BUZZ bandgap
0018 OSC_CR0_SLEEP: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_SLEEP_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_SLEEP_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_SLEEP_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_SLEEP_1Hz: equ 18h ; Set sleep bits for 1 sec period
0000
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0000
0000 ;------------------------------------------------------
0000 ; Note: The following registers are mapped into both
0000 ; register bank 0 AND register bank 1.
0000 ;------------------------------------------------------
00F7 CPU_F: equ F7h ; CPU Flag Register Access (RO)
0000 ; Use FLAG_ masks defined at top of file
00FF CPU_SCR: equ FFh ; CPU Status and Control Register (#)
0080 CPU_SCR_GIE_MASK: equ 80h ; MASK: Global Interrupt Enable shadow
0020 CPU_SCR_WDRS_MASK: equ 20h ; MASK: Watch Dog Timer Reset
0010 CPU_SCR_PORS_MASK: equ 10h ; MASK: power-on reset bit PORS
0008 CPU_SCR_SLEEP_MASK: equ 08h ; MASK: Enable Sleep
0001 CPU_SCR_STOP_MASK: equ 01h ; MASK: Halt CPU bit
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 1
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Clock and System Control Registers
0000 ;------------------------------------------------
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 mov reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR], ~CPU_SCR_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPU_SCR_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPU_SCR_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
0000 MACRO GET_WORD
0000 PUSH A ; Quickly get a RAM temp
0000 PUSH A ; Save the source MSB
0000 ROMX ; Get the first byte
0000 PUSH X ; Save X
0000 MOV X,SP ; Get SP, to index to the temp
0000 MOV [X - 3],A ; Save the first byte
0000 POP X ; Get back the source LSB
0000 POP A ; And the MSB
0000 INC X ; Point to the second byte
0000 ADC A, 0 ;
0000 ROMX ; Get the second byte
0000 MOV X,A ; Save it in X
0000 POP A ; And the first byte in A
0000 MACRO NULL_PTR_CHECK
0000 SWAP A, X ; LSB non-zero?
0000 JNZ .ok ; Exit on non-zero
0000 SWAP A, X ; MSB zero
0000 JZ @0 ; Jump to the null pointer handler
0000 JMP .exit
0000 .ok:
0000 SWAP A, X ; Put them back
0000 .exit:
0000 NULL_PTR: EQU 0 ; Null pointer value
0000
0000 ;--------------------------------------------------
0000 ; Transfer Descriptor--Data Source
0000 ;--------------------------------------------------
0000 USB_DS_ROM: EQU 0x00
0001 USB_DS_RAM: EQU 0x01
0002 USB_DS_RAM_CB: EQU 0x02
0003 USB_DS_RAM_MASK: EQU 0x03
0000
0000 ;--------------------------------------------------
0000 ; TRANSFER DESCRIPTOR MACROS
0000 ;--------------------------------------------------
0000
0000 ;-----------------------------------------------
0000 ; TD_START_TABLE MACRO
0000 ;-----------------------------------------------
0000 ; Parameters:
0000 ; @0 = Number of table entries
0000 ; Register setup
0000 ; N/A (builds ROM data at assembly time)
0000 ;-----------------------------------------------
0000 MACRO TD_START_TABLE
0000 DB ((@0) - 1) ; Number of table entries - 1
0000 MACRO TD_ENTRY
0000 DB @0 ; Data source (USB_DS_*)
0000 DW @1 ; Transfer size
0000 DW @2 ; Data source address
0000 DW @3 ; Transfer Completion Status Block Address
0000 DB 0xde ; Reserved
0008 TD_ENTRY_SIZE: EQU 8
0001 TD_START_SIZE: EQU 1
0000 ;-----------------------------------------------
0000 ; TD_INDEX_TO_OFFSET MACRO
0000 ;-----------------------------------------------
0000 ; Parameters:
0000 ; @0 = RAM address of Index
0000 ; Register setup
0000 ; A = DC (restored)
0000 ; X = DC (not used)
0000 ;--------------------------------------------------
0000 MACRO TD_INDEX_TO_OFFSET
0000 PUSH A ; Save a work register
0000 ASL [@0] ; Index * 2
0000 ASL [@0] ; Index * 4
0000 ASL [@0] ; Index * 4
0000 POP A ; Restore the work register
0000 MACRO LT_START
0000 DB (@0) ; Table size
0000 MACRO LT_ENTRY
0000 DW (@0) ; Table entry
0000 DW (@1) ; Table entry
0002 LT_ENTRY_SIZE: EQU 2
0001 LT_START_SIZE: EQU 1
0000
0000 ;-----------------------------------------------
0000 ; LT_INDEX_TO_OFFSET MACRO
0000 ;-----------------------------------------------
0000 ; Parameters:
0000 ; @0 = RAM address of Index
0000 ; Register setup
0000 ; A = DC (not used)
0000 ; X = DC (not used)
0000 ;--------------------------------------------------
0000 MACRO LT_INDEX_TO_OFFSET
0000 ASL [@0] ; Simply shift (mult by 2)
0000 ASL [@0] ; (mult by 4)
0000 MACRO DISPATCHER
0000 CMP A,@1
0000 JNC .dispatch_not_supported
0000 ASL A
0000 JACC @0
0000 .dispatch_not_supported:
0000 JMP @2
0001 USB_NOT_SUPPORTED: EQU 0x01
0002 USB_UM_SUPPLIED: EQU 0x02
0004 USB_APP_SUPPLIED: EQU 0x04
0000 ; end of file USB_macro.inc
0000 USB_bNumStringDescrs: EQU 0
0000
0003 USB_NUM_ENDPOINTS: EQU 3
0002 USB_MAX_EP_NUMBER: EQU (USB_NUM_ENDPOINTS - 1)
0000
0000 ;--------------------------------------------------
0000 ; Registers for USB API's.
0000 ;--------------------------------------------------
0074 USB_USBXCR: EQU USBXCR
0040 USB_ADDR: EQU USBCR
0041 USB_EP0CNT: EQU EP0CNT
0042 USB_EP1CNT: EQU (EP0CNT + 1)
0043 USB_EP2CNT: EQU (EP0CNT + 2)
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