?? hw_sysctl.h
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//*****************************************************************************
//
// hw_sysctl.h - Macros used when accessing the system control hardware.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1392 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_SYSCTL_H__
#define __HW_SYSCTL_H__
//*****************************************************************************
//
// The following define the addresses of the system control registers.
//
//*****************************************************************************
#define SYSCTL_DID0 0x400fe000 // Device identification register 0
#define SYSCTL_DID1 0x400fe004 // Device identification register 1
#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0
#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1
#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2
#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3
#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4
#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register
#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register
#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0
#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1
#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2
#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register
#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register
#define SYSCTL_MISC 0x400fe058 // Interrupt status register
#define SYSCTL_RESC 0x400fe05c // Reset cause register
#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register
#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register
#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2
#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0
#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1
#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2
#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0
#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1
#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2
#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0
#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1
#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2
#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg
#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register
#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register
#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0
#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DID0 register.
//
//*****************************************************************************
#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask
#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0
#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1
#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class
#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device
#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device
#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C
#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0
#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1
#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2
#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3
#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4
#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DID1 register.
//
//*****************************************************************************
#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301
#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310
#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315
#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316
#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317
#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328
#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601
#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610
#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611
#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612
#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613
#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615
#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617
#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618
#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628
#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801
#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811
#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812
#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815
#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817
#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818
#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828
#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110
#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139
#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410
#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412
#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432
#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533
#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620
#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637
#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651
#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730
#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739
#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939
#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948
#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950
#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965
#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100
#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110
#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420
#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422
#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432
#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610
#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633
#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637
#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730
#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938
#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952
#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count
#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package
#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)
#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)
#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC
#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP
#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant
#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)
#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)
#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified
#define SYSCTL_DID1_PRTNO_SHIFT 16
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC0 register.
//
//*****************************************************************************
#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash
#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash
#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash
#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash
#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash
#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC1 register.
//
//*****************************************************************************
#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present
#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present
#define SYSCTL_DC1_PWM 0x00100000 // PWM module present
#define SYSCTL_DC1_ADC 0x00010000 // ADC module present
#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC
#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC
#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC
#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present
#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present
#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present
#define SYSCTL_DC1_PLL 0x00000010 // PLL present
#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC2 register.
//
//*****************************************************************************
#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present
#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
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