//
    // Make sure that the address passed in is valid.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));

    //
    // Clear the init bit in the control register.
    //
    CANWriteReg(ulBase + CAN_O_CTL,
                CANReadReg(ulBase + CAN_O_CTL) & ~CAN_CTL_INIT);
}

//*****************************************************************************
//
//! Disables the CAN controller.
//!
//! \param ulBase is the base address of the CAN controller to disable.
//!
//! Disables the CAN controller for message processing.  When disabled, the
//! controller will no longer automatically process data on the CAN bus.
//! The controller can be restarted by calling CANEnable().  The state of the
//! CAN controller and the message objects in the controller are left as they
//! were before this call was made.
//!
//! \return None.
//
//*****************************************************************************
void
CANDisable(unsigned long ulBase)
{
    //
    // Make sure that the address passed in is valid.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));

    //
    // Set the init bit in the control register.
    //
    CANWriteReg(ulBase + CAN_O_CTL,
                CANReadReg(ulBase + CAN_O_CTL) | CAN_CTL_INIT);
}

//*****************************************************************************
//
//! Reads the current settings for the CAN controller bit timing.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param pClkParms is a pointer to a structure to hold the timing parameters.
//!
//! This function reads the current configuration of the CAN controller bit
//! clock timing, and stores the resulting information in the structure
//! supplied by the caller.  Refer to CANSetBitTiming() for the meaning of the
//! values that are returned in the structure pointed to by \e pClkParms.
//!
//! \return None.
//
//*****************************************************************************
void
CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms)
{
    unsigned int uBitReg;

    //
    // Make sure that the address passed in is valid and the pointer is not
    // NULL.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));
    ASSERT(pClkParms != 0);

    //
    // Read out all the bit timing values from the CAN controller registers.
    //
    uBitReg = CANReadReg(ulBase + CAN_O_BIT);

    //
    // Set the phase 2 segment.
    //
    pClkParms->uPhase2Seg = ((uBitReg & CAN_BIT_TSEG2) >> 12) + 1;

    //
    // Set the phase 1 segment.
    //
    pClkParms->uSyncPropPhase1Seg = ((uBitReg & CAN_BIT_TSEG1) >> 8) + 1;

    //
    // Set the sychronous jump width.
    //
    pClkParms->uSJW = ((uBitReg & CAN_BIT_SJW) >> 6) + 1;

    //
    // Set the pre-divider for the CAN bus bit clock.
    //
    pClkParms->uQuantumPrescaler =
        ((uBitReg & CAN_BIT_BRP) |
        ((CANReadReg(ulBase + CAN_O_BRPE) & CAN_BRPE_BRPE) << 6)) + 1;
}

//*****************************************************************************
//
//! Configures the CAN controller bit timing.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param pClkParms points to the structure with the clock parameters
//!
//! Configures the various timing parameters for the CAN bus bit timing:
//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and
//! the Synchronization Jump Width.  The values for Propagation and Phase
//! Buffer 1 segments are derived from the combination parameter
//! \e pClkParms->uSyncPropPhase1Seg.  Phase Buffer 2 is determined from the
//! parameter \e pClkParms->uPhase2Seg.  These two parameters, along with
//! \e pClkParms->uSJW are based in units of bit time quanta.
//! The actual quantum time is determined by the
//! \e pClkParms->uQuantumPrescaler value, which specifies what the divisor for
//! the CAN module clock.
//!
//! The total bit time, in quanta, will be the sum of the two Seg
//! parameters, as follows:
//!
//! bit_time_q = uSyncPropPhase1Seg + uPhase2Seg + 1
//!
//! Note that the Sync_Seg is always one quantum in duration, and will be
//! added to derive the correct duration of Prop_Seg and Phase1_Seg.
//!
//! The equation to determine the actual bit rate is as follows:
//!
//! CAN Clock /
//! ((\e uSyncPropPhase1Seg + \e uPhase2Seg + 1)*(\e uQuantumPrescaler))
//!
//! This means that with \e uSyncPropPhase1Seg = 4, \e uPhase2Seg = 1,
//! \e uQuantumPrescaler = 2 and a 8MHz CAN clock, that the bit rate will be
//! (8MHz)/((5 + 2 + 1)*2) or 500 KBit/sec.
//!
//! \return None.
//
//*****************************************************************************
void
CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms)
{
    unsigned int uBitReg;
    unsigned int uSavedInit;

    //
    // Make sure that the address passed in is valid and the pClkParms is not
    // NULL.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));
    ASSERT(pClkParms != 0);

    //
    // The phase 1 segment must be in the range from 2 to 16.
    //
    ASSERT((pClkParms->uSyncPropPhase1Seg >= 2) &&
           (pClkParms->uSyncPropPhase1Seg <= 16));

    //
    // The phase 2 segment must be in the range from 1 to 8.
    //
    ASSERT((pClkParms->uPhase2Seg >= 1) && (pClkParms->uPhase2Seg <= 8));

    //
    // The synchronous jump windows must be in the range from 1 to 4.
    //
    ASSERT((pClkParms->uSJW >= 1) && (pClkParms->uSJW <= 4));

    //
    // The CAN clock pre-divider must be in the range from 1 to 1024.
    //
    ASSERT((pClkParms->uQuantumPrescaler <= 1024) &&
           (pClkParms->uQuantumPrescaler >= 1));

    //
    // To set the bit timing register, the controller must be placed
    // in init mode (if not already), and also configuration change
    // bit enabled.  State of the init bit should be saved so it can
    // be restored at the end.
    //
    uSavedInit = CANReadReg(ulBase + CAN_O_CTL);
    CANWriteReg(ulBase + CAN_O_CTL, uSavedInit | CAN_CTL_INIT | CAN_CTL_CCE);

    //
    // Set the bit fields of the bit timing register according to the parms
    //
    uBitReg = ((pClkParms->uPhase2Seg - 1) << 12) & CAN_BIT_TSEG2;
    uBitReg |= ((pClkParms->uSyncPropPhase1Seg - 1) << 8) & CAN_BIT_TSEG1;
    uBitReg |= ((pClkParms->uSJW - 1) << 6) & CAN_BIT_SJW;
    uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BIT_BRP;
    CANWriteReg(ulBase + CAN_O_BIT, uBitReg);

    //
    // Set the divider upper bits in the extension register
    //
    CANWriteReg(ulBase + CAN_O_BRPE,
                ((pClkParms->uQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE);
    //
    // Clear the config change bit, and restore the init bit
    //
    uSavedInit &= ~CAN_CTL_CCE;

    //
    // If Init was not set before, then clear it.
    //
    if(uSavedInit & CAN_CTL_INIT)
    {
        uSavedInit &= ~CAN_CTL_INIT;
    }
    CANWriteReg(ulBase + CAN_O_CTL, uSavedInit);
}

//*****************************************************************************
//
//! Returns the CAN controller interrupt number.
//!
//! \param ulBase is the base address of the selected CAN controller
//!
//! Given a CAN controller base address, returns the corresponding interrupt
//! number.
//!
//! \return Returns a CAN interrupt number, or -1 if \e ulPort is invalid.
//
//*****************************************************************************
long
CANGetIntNumber(unsigned long ulBase)
{
    long lIntNumber;

    //
    // Return the interrupt number for the given CAN controller.
    //
    switch(ulBase)
    {
        //
        // Return the interrupt number for CAN 0
        //
        case CAN0_BASE:
        {
            lIntNumber = INT_CAN0;
            break;
        }

        //
        // Return the interrupt number for CAN 1
        //
        case CAN1_BASE:
        {
            lIntNumber = INT_CAN1;
            break;
        }

        //
        // Return -1 to indicate a bad address was passed in.
        //
        default:
        {
            lIntNumber = -1;
        }
    }
    return(lIntNumber);
}

//*****************************************************************************
//
//! Registers an interrupt handler for the CAN controller.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param pfnHandler is a pointer to the function to be called when the
//! enabled CAN interrupts occur.
//!
//! This function registers the interrupt handler in the interrupt vector
//! table, and enables CAN interrupts on the interrupt controller; specific
//! CAN interrupt sources must be enabled using CANIntEnable().  The
//! interrupt handler being registered must clear the source of the interrupt
//! using CANIntClear();
//!
//! If the application is using a static interrupt vector table stored
//! in flash, then it is not necessary to register the interrupt handler
//! this way.  Instead, IntEnable() should be used to enable CAN interrupts
//! on the interrupt controller.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
    unsigned long ulIntNumber;

    //
    // Make sure that the address passed in is valid.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));

    //
    // Get the actual interrupt number for this CAN controller.
    //
    ulIntNumber = CANGetIntNumber(ulBase);

    //
    // Register the interrupt handler.
    //
    IntRegister(ulIntNumber, pfnHandler);

    //
    // Enable the Ethernet interrupt.
    //
    IntEnable(ulIntNumber);
}

//*****************************************************************************
//
//! Unregisters an interrupt handler for the CAN controller.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function unregisters the previously registered interrupt handler
//! and disables the interrupt on the interrupt controller.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
CANIntUnregister(unsigned long ulBase)
{
    unsigned long ulIntNumber;

    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));

    //
    // Get the actual interrupt number for this CAN controller.
    //
    ulIntNumber = CANGetIntNumber(ulBase);

    //
    // Register the interrupt handler.
    //
    IntUnregister(ulIntNumber);

    //
    // Disable the CAN interrupt.
    //
    IntDisable(ulIntNumber);
}

//*****************************************************************************
//
//! Enables individual CAN controller interrupt sources.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables specific interrupt sources of the CAN controller.  Only enabled
//! sources will cause a processor interrupt.
//!
//! The parameter \e ulIntFlags is the logical OR of any of the following:
//!
//! - CAN_INT_ERROR - controller error condition has occurred
//! - CAN_INT_STATUS - a message transfer completed, or bus error detected
//! - CAN_INT_MASTER - allow CAN controller to generate interrupts
//!
//! In order to generate any interrupts, CAN_INT_MASTER must be enabled.
//! Further, for any particular transaction from a message object to
//! generate an interrupt, that message object must have interrupts enabled
//! (see CANMessageSet()).  CAN_INT_ERROR will generate an interrupt if the
//! controller enters the "bus off" condition, or if the error counters reach a
//! limit.  CAN_INT_STATUS will generate an interrupt under quite a few status
//! conditions and may provide more interrupts than the application needs to
//! handle.  When an interrupt occurs, use CANIntStatus() to determine the
//! cause.
//!
//! \return None.
//
//*****************************************************************************
void
CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //