// Interrupt registers
//
#define INT_SPRT0          (CTL_OFF+OFFS_INT_SPRT0)
#define INT_SPRT1          (CTL_OFF+OFFS_INT_SPRT1)  //ES
#define INT_SPRT           (CTL_OFF+OFFS_INT_SPRT)
#define INT_WDOG_EM        (CTL_OFF+OFFS_INT_WDOG_EM)
//
#define INT_INT4           (CTL_OFF+OFFS_INT_INT4)
#define INT_INT3           (CTL_OFF+OFFS_INT_INT3)
#define INT_INT2           (CTL_OFF+OFFS_INT_INT2)
#define INT_INT1           (CTL_OFF+OFFS_INT_INT1)
#define INT_INT0           (CTL_OFF+OFFS_INT_INT0)

#define INT_DMA1           (CTL_OFF+OFFS_INT_DMA1)
#define INT_DMA0           (CTL_OFF+OFFS_INT_DMA0)
#define INT_INT6           (CTL_OFF+OFFS_INT_INT6)
#define INT_INT5           (CTL_OFF+OFFS_INT_INT5)

#define INT_TMR            (CTL_OFF+OFFS_INT_TMR)

#define INT_STAT           (CTL_OFF+OFFS_INT_STAT)
#define INT_IREQ           (CTL_OFF+OFFS_INT_IREQ)
#define INT_INSV           (CTL_OFF+OFFS_INT_INSV)
#define INT_PMSK           (CTL_OFF+OFFS_INT_PMSK)
#define INT_MASK           (CTL_OFF+OFFS_INT_MASK)
#define INT_PSTT           (CTL_OFF+OFFS_INT_PSTT)
#define INT_POLL           (CTL_OFF+OFFS_INT_POLL)
#define INT_EOI            (CTL_OFF+OFFS_INT_EOI)
#define INT_VEC            (CTL_OFF+OFFS_INT_VEC)
//
// ES Serial port 1 register
// EM/ER Synchronous serial port register
//
#define SPRT1_BDV          (CTL_OFF+OFFS_SPRT1_BDV)
#define SPRT1_RX           (CTL_OFF+OFFS_SPRT1_RX)
#define SPRT1_TX           (CTL_OFF+OFFS_SPRT1_TX)
#define SPRT1_STAT         (CTL_OFF+OFFS_SPRT1_STAT)
#define SPRT1_CTL          (CTL_OFF+OFFS_SPRT1_CTL)

#define SS_RX              (CTL_OFF+OFFS_SS_RX)
#define SS_TX0             (CTL_OFF+OFFS_SS_TX0)
#define SS_TX1             (CTL_OFF+OFFS_SS_TX1)
#define SS_CTL             (CTL_OFF+OFFS_SS_CTL)
#define SS_STAT            (CTL_OFF+OFFS_SS_STAT)

// =======================================================================
// Internal Register field definitions

// RELOCATION REGISTER

#define REL_REG_SLAVE      0x4000         // slave interrupt controls
#define REL_REG_MEMSPACE   0x1000         // PCB in memory space

// --------------------------------------------------------------
// Processor release level (PRL_REG - offset 0xf4)

#define PRL_REG_ES_REVA    0x1000          //  Am188ES
#define PRL_REG_ER_REVA8   0x2100          //  Am188ER 
#define PRL_REG_ER_REVA6   0x2000          //  Am186ER 
#define PRL_REG_EM_REVC    0x0100          //  Am186EM 
#define PRL_REG_EM_REVD    0x0200          //  Am186EM 
#define PRL_REG_EM_REVE    0x0300          //  Am186EM 
#define PRL_REG_EM_REVF    0x0400          //  Am186EM 
#define PRL_REG_EM_REVG    0x0500          //  Am186EM 


// --------------------------------------------------------------
// Power-save control register (PDCN_REG or SYSCON - offset 0xf0)

#define PDCN_REG_PSEN      0x8000          //  Power-save enable bit
#define PDCN_REG_MCSBIT    0x4000          //  Power-save enable bit
#define PDCN_REG_DSDEN     0x2000          //  Power-save enable bit
#define PDCN_REG_PWD       0x1000          //  Power-save enable bit
#define PDCN_REG_CBF       0x0800          //  CLKOUTB Output Frequency
#define PDCN_REG_CBD       0x0400          //  CLKOUTB Drive Disable
#define PDCN_REG_CAF       0x0200          //  CLKOUTA Output Frequency
#define PDCN_REG_CAD       0x0100          //  CLKOUTA Drive Disable
#define PDCN_REG_CDIV1     0x0000          //  clock div factor = 1
#define PDCN_REG_CDIV2     0x0001          //  clock div factor = 2
#define PDCN_REG_CDIV4     0x0002          //  clock div factor = 4
#define PDCN_REG_CDIV8     0x0003          //  clock div factor = 8
#define PDCN_REG_CDIV16    0x0004          //  clock div factor = 16
#define PDCN_REG_CDIV32    0x0005          //  clock div factor = 32
#define PDCN_REG_CDIV64    0x0006          //  clock div factor = 64
#define PDCN_REG_CDIV128   0x0007          //  clock div factor = 128
//
// RAM refresh control
//
#define DRAM_ENABLE        0x8000          //  enable bit for DRAM
//
// --------------------------------------------------------------
// INTERRUPT IN-SERVICE REGISTER BITS (INSERV - 0x2c)
//
#define INT_INSV_SPRT0     0x0400          //  serial port 0x
#define INT_INSV_SPRT1     0x0200          //  serial port 1
#define INT_INSV_INT4      0x0100          //  external int 4
#define INT_INSV_INT3      0x0080          //  external int 3
#define INT_INSV_INT2      0x0040          //  external int 2
#define INT_INSV_INT1      0x0020          //  external int 1
#define INT_INSV_INT0      0x0010          //  external int 0x
#define INT_INSV_DMA1      0x0008          //  DMA1
#define INT_INSV_INT6      0x0008          //  ES INT6 same as DMA1
#define INT_INSV_DMA0      0x0004          //  DMA0
#define INT_INSV_INT5      0x0004          //  ES INT5 same as DMA0
#define INT_INSV_TMR       0x0001          //  all of the timers (except WDOG)

// -------------------------------------------------------------
// INTERRUPT REQUEST REGISTER BITS (REQST - 0x2e)
#define INT_REQ_SPRT0      INT_INSV_SP0
#define INT_REQ_SPRT1      INT_INSV_SP1
#define INT_REQ_INT4       INT_INSV_INT4
#define INT_REQ_INT3       INT_INSV_INT3
#define INT_REQ_INT2       INT_INSV_INT2
#define INT_REQ_INT1       INT_INSV_INT1
#define INT_REQ_INT0       INT_INSV_INT0
#define INT_REQ_DMA1       INT_INSV_DMA1
#define INT_REQ_INT6       INT_INSV_INT6
#define INT_REQ_DMA0       INT_INSV_DMA0
#define INT_REQ_INT5       INT_INSV_INT5
#define INT_REQ_TMR        INT_INSV_TMR
//
// -------------------------------------------------------------
// PIO PINS
#define PIO0_TMRI1         0x0001    // PIO 0
#define PIO0_TMRO1         0x0002    // PIO 1
#define PIO0_PCS6          0x0004    // PIO 2
#define PIO0_PCS5          0x0008    // PIO 3
#define PIO0_DTR           0x0010    // PIO 4
#define PIO0_DEN           0x0020    // PIO 5
#define PIO0_SRDY          0x0040    // PIO 6
#define PIO0_A17           0x0080    // PIO 7
#define PIO0_A18           0x0100    // PIO 8
#define PIO0_A19           0x0200    // PIO 9
#define PIO0_TMRO0         0x0400    // PIO 10
#define PIO0_TMRI0         0x0800    // PIO 11
#define PIO0_DRQ0          0x1000    // PIO 12
#define PIO0_DRQ1          0x2000    // PIO 13
#define PIO0_MCS0          0x4000    // PIO 14
#define PIO0_MCS1          0x8000    // PIO 15

#define PIO1_PCS0          0x0001    // PIO 16
#define PIO1_PCS1          0x0002    // PIO 17
#define PIO1_PCS2          0x0004    // PIO 18
#define PIO1_PCS3          0x0008    // PIO 19
#define PIO1_RTS0          0x0010    // PIO 20 on ES
#define PIO1_CTS0          0x0020    // PIO 21 on ES
#define PIO1_SCLK          0x0010    // PIO 20 on EM/ER
#define PIO1_SDATA         0x0020    // PIO 21 on EM/ER
#define PIO1_TX0           0x0040    // PIO 22 on ES
#define PIO1_RX0           0x0080    // PIO 23 on ES
#define PIO1_SDEN0         0x0040    // PIO 22 on EM/ER
#define PIO1_SDEN1         0x0080    // PIO 23 on EM/ER
#define PIO1_MCS2          0x0100    // PIO 24
#define PIO1_MCS3          0x0200    // PIO 25
#define PIO1_UZI           0x0400    // PIO 26
#define PIO1_TX            0x0800    // PIO 27
#define PIO1_RX            0x1000    // PIO 28
#define PIO1_TX1           0x0800    // PIO 27
#define PIO1_RX1           0x1000    // PIO 28
#define PIO1_S6            0x2000    // PIO 29
#define PIO1_INT4          0x4000    // PIO 30
#define PIO1_INT2          0x8000    // PIO 31
//
//
// Asynchronous serial port control register (SPRT_CTL)
//
//  -------------------------------------------------------------
//  SERIAL PORT CONTROL REGISTERS (1&2 - 0x80, 0x10)
//  DMA bits -- ES ONLY
#define SPRT_CTL_RD0_TD1  0x2000    //  Receive DMA0, Transmit DMA1
#define SPRT_CTL_RD1_TD0  0x4000    //  Receive DMA1, Transmit DMA0
#define SPRT_CTL_RD0_TOFF 0x8000    //  Receive DMA0, Transmit off
#define SPRT_CTL_RD1_TOFF 0xA000    //  Receive DMA1, Transmit off
#define SPRT_CTL_ROFF_TD0 0xC000    //  Receive off, Transmit DMA0
#define SPRT_CTL_ROFF_TD1 0xE000    //  Receive off, Transmit DMA1
//
// Other serial port bits -- EM/ER only
//
#define SPRT_CTL_TXIE_EM      0x0800   //  enable transmit intrpt
#define SPRT_CTL_RXIE_EM      0x0400   //  enable receive intrpt
#define SPRT_CTL_LOOP_EM      0x0200   //  enable loop-back mode
#define SPRT_CTL_BRK_EM       0x0100   //  send break or *break
#define SPRT_CTL_BRKHIGH_EM   0x0080   //  break value is high
#define SPRT_CTL_BRKLOW_EM    0x0000   //  break value is low
#define SPRT_CTL_NOPARITY_EM  0x0000   //  no parity bit
#define SPRT_CTL_EVEN_EM      0x0060   //  even parity
#define SPRT_CTL_ODD_EM       0x0040   //  odd parity
#define SPRT_CTL_8BITS_EM     0x0010   //  char lengt is 8 bits
#define SPRT_CTL_7BITS_EM     0x0000   //  char lengt is 7 bits
#define SPRT_CTL_2STOP_EM     0x0008   //  two stop bits
#define SPRT_CTL_1STOP_EM     0x0000   //  one stop bit
#define SPRT_CTL_TX_EM        0x0004   //  enable transmitter
#define SPRT_CTL_RSIE_EM      0x0002   //  enable Rx error intrpts
#define SPRT_CTL_RX_EM        0x0001   //  enable receiver
//
//
// Other serial port bits -- ES Only
//
#define SPRT_CTL_RSIE_ES      0x1000   //  enable Rx status interrupts
#define SPRT_CTL_BRK_ES       0x0800   //  send break
#define SPRT_CTL_TB8_ES       0x0400   //  Transmit data bit 8
#define SPRT_CTL_HS_ES        0x0200   //  hardware handshake enable
#define SPRT_CTL_TXIE_ES      0x0100   //  enable transmit interrupt
#define SPRT_CTL_RXIE_ES      0x0080   //  enable receive interrupt
#define SPRT_CTL_TMODE_ES     0x0040   //  enable transmitter
#define SPRT_CTL_RMODE_ES     0x0020   //  enable receiver 
#define SPRT_CTL_EVN_ES       0x0010   //  even parity
#define SPRT_CTL_PE_ES        0x0008   //  enable parity checking
#define SPRT_CTL_MODE1_ES     0x0001   //  Async. mode A
#define SPRT_CTL_MODE2_ES     0x0002   //  Async. address recog. mode
#define SPRT_CTL_MODE3_ES     0x0003   //  Async. mode B
#define SPRT_CTL_MODE4_ES     0x0004   //  Async. mode C
//
// Asynchronous serial port status register (SPRT_STAT) EM/ER
//
#define SPRT_STAT_TEMT_EM     0x0040   //  transmitter is empty
#define SPRT_STAT_THRE_EM     0x0020   //  Tx holding reg. empty
#define SPRT_STAT_RDR_EM      0x0010   //  receive char ready
#define SPRT_STAT_BRK_EM      0x0008   //  break received
#define SPRT_STAT_FRAME_EM    0x0004   //  framing error detected
#define SPRT_STAT_PARITY_EM   0x0002   //  parity error detected
#define SPRT_STAT_OVERFLOW_EM 0x0001   //  receive overflow
//
// Asynchronous serial port status register (SPRT_STAT) ES only
//
#define SPRT_STAT_BRK1_ES     0x0400  //  Long break detected
#define SPRT_STAT_BRK0_ES     0x0200  //  Short break detected
#define SPRT_STAT_RB8_ES      0x0100  //  Receive data bit 9
#define SPRT_STAT_RDR_ES      0x0080  //  Receive data ready
#define SPRT_STAT_THRE_ES     0x0040  //  Tx holding reg. empty
#define SPRT_STAT_FRAME_ES    0x0020  //  Framing error detected
#define SPRT_STAT_OVERFLOW_ES 0x0010  //  Overrun error detected
#define SPRT_STAT_PARITY_ES   0x0008  //  Parity error detected
#define SPRT_STAT_TEMT_ES     0x0004  //  transmitter is empty
#define SPRT_STAT_HS0_ES      0x0002  //  *CTS signal asserted
//
//  all Sbreaks must set this bit
#define SPRT_STAT_BRK_ES    SPRT_STAT_BRK0_ES


// -----------------------------------------------------------------------
// DMA Control Registers (1&2 - 0xda, 0xca)

#define DMA_DEST_MEM       0x8000   // DMA dest. 1=memory, 0=I/O space
#define DMA_DEST_DEC       0x4000   // decrement DMA dest addr
#define DMA_DEST_INC       0x2000   // increment DMA dest addr
#define DMA_SRC_MEM        0x1000   // DMA source 1=memory, 0=I/O space
#define DMA_SRC_DEC        0x0800   // decrement DMA src addr
#define DMA_SRC_INC        0x0400   // increment DMA src addr
#define DMA_TC             0x0200   // DMA uses terminal count
#define DMA_INT            0x0100   // intrpt on terminal count
#define DMA_SYN1           0x0080   // 1=Src. Sync.2=Dest. Sync.3=Undef.
#define DMA_SYN0           0x0040   // SYN1:0 0x = Unsynchronized
#define DMA_P              0x0020   // if set, channel=hi prio.,else low
#define DMA_IDRQ           0x0010   // if set, use timer 2
#define DMA_EXT            0x0008   // (ES only) if set, DRQ used for ext. int.
#define DMA_CHG            0x0004   // set before DMA_STRT can be set
#define DMA_STRT           0x0002   // if set, DMA channel is "armed"
#define DMA_WORD           0x0001   // if set, word transfers, else byte
#define DMA_BYTE           0x0000   // Byte transfers
// some common combinations
#define DMA_S_MEM_INC      DMA_SRC_MEM+DMA_SRC_INC
#define DMA_D_MEM_INC      DMA_DEST_MEM+DMA_DEST_INC
#define DMA_S_D_MEM_INC    DMA_S_MEM_INC+DMA_D_MEM_INC
#define DMA_ARM            DMA_CHG+DMA_STRT

#define DMA_DEST_CONST     0x0000   //  DMA destination addr is constant
#define DMA_SRC_IO         0x0000   //  DMA source is in I/O space