#define DMA_SRC_CONST      0x0000   //  DMA source addr is constant
#define DMA_DEST_IO        0x0000   //  DMA destination is in I/O space
#define DMA_UNSYNC         0x0000   //  unsynchronized transfers
#define DMA_SRCSYNC        0x00c0   //  source synchronized transfers
#define DMA_DESTSYNC       0x0080   //  destination synchronized transfers
#define DMA_HIGHPRI        0x0040   //  channel is high priority
#define DMA_LOWPRI         0x0000   //  channel is low priority
// 
// -------------------------------------------------------------
// CHIP-SELECT REGISTERS

// Fields used by more than one of the chip select registers
#define CS_WAIT0           0x0000   //  zero wait states
#define CS_WAIT1           0x0001   //  one wait state
#define CS_WAIT2           0x0002   //  two wait states
#define CS_WAIT3           0x0003   //  three wait states
#define CS_IGXRDY          0x0004   //  ignore external ready
// The following wait states can only be used for PCS3-0 - set in
// the PACS register (CS_PACS).
//
#define CS_MPCS_WAIT5      0x0008   //  five wait states
#define CS_MPCS_WAIT7      0x0009   //  seven wait states
#define CS_MPCS_WAIT9      0x000a   //  nine wait states
#define CS_MPCS_WAIT15     0x000b   //  fifteen wait states

// The following bit is only on LCS (CS_LMCS) and UCS (CS_UMCS)
#define CS_DISADDR         0x0080   //  disable AD addr output
//
// UMCS (upper memory) register
#define CS_UMCS_64K        0x7000   //  UCS is 64K
#define CS_UMCS_128K       0x6000   //  UCS is 128K
#define CS_UMCS_256K       0x4000   //  UCS is 256K
#define CS_UMCS_512K       0x0000   //  UCS is 512K
//
// LMCS (lower memory) register
#define CS_LMCS_PSRAM      0x0040   // turn off PSRAM when subtracted out
#define CS_LMCS_64K        0x0000   //  LCS is 64K  (0 - 0ffffh)
#define CS_LMCS_128K       0x1000   //  LCS is 128K (0 - 1ffffh)
#define CS_LMCS_256K       0x3000   //  LCS is 256K (0 - 3ffffh)
#define CS_LMCS_512K       0x7000   //  LCS is 512K (0 - 7ffffh)
#define CS_LMCS_PSEN       0x0040   //  enable PSRAM support

// IMCS (internal memory) register	(Am186ER)
#define CS_IMCS_SHOW_READ  0x0040   //  show read enable
#define CS_IMCS_RAM_ENABLE 0x0200	//  internal ram enable
#define CS_IMCS_RESERVED   0x00ff	//  reserved bits with a 1 value

// MPCS specific register bits
#define CS_MPCS_EX         0x0080
#define CS_MPCS_MS         0x0040
#define CS_MPCS_EXWT       0x0008   //  EXTENDED PCS WAIT STATES
#define CS_MPCS_8K         0x0100
#define CS_MPCS_16K        0x0200
#define CS_MPCS_32K        0x0400
#define CS_MPCS_64K        0x0800
#define CS_MPCS_128K       0x1000
#define CS_MPCS_256K       0x2000
#define CS_MPCS_512K       0x4000
#define CS_MPCS_PCS_ADDR   0x0000   //  PCS6-5 are addr lines
#define CS_MPCS_RESERVED   0x8038   // reserved bits with a 1 value 

// PACS specific register bits
#define CS_PACS_RESERVED   0x0070	// reserved bits with a 1 value
				
//
// -------------------------------------------------------------
// Timer register (1&2 - 0x56, 0x5e)
#define TMR_ENABLE         0x8000
#define TMR_INH            0x4000
#define TMR_INT            0x2000   //  generate intrpt rest
#define TMR_RIU            0x1000   //  ax count reached flag
#define TMR_MC             0x0020   //  max count reached flag
#define TMR_RTG            0x0010   //  retrigger bit
#define TMR_2PRES          0x0008   //  timer 2 is a prescaler
#define TMR_EXT            0x0004   //  use external timer
#define TMR_ALT            0x0002
#define TMR_CONT           0x0001   //  continuous mode
#define TMR_START          TMR_ENABLE+TMR_INH     //  start timer
// These fields apply to master mode interrupt control registers
// Priorities also apply to interrupt priority register (INT_PMSK)
#define INT_PRI0           0x0000   //  highest priority
#define INT_PRI1           0x0001   //  priority = 1
#define INT_PRI2           0x0002   //  priority = 2
#define INT_PRI3           0x0003   //  priority = 3
#define INT_PRI4           0x0004   //  priority = 4
#define INT_PRI5           0x0005   //  priority = 5
#define INT_PRI6           0x0006   //  priority = 6
#define INT_PRI7           0x0007   //  lowest priority
#define INT_DISABLE        0x0008   //  disable interrupt
#define INT_ENABLE         0x0000   //  enable interrupt
#define INT_LEVEL          0x0010   //  level triggered mode
#define INT_EDGE           0x0000   //  edge triggered mode

// These two fields apply only to INT_INT0 and INT_INT1

#define INT_CASCADE        0x0020   //  cascade mode enable
#define INT_SFNM           0x0040   //  specl fully nested mode
// Interrupt Status Register fields (INT_STAT)
#define INT_DHLT           0x8000   //  halt DMA activity
#define INT_STAT_TMR2      0x0004   //  TMR2 has intrpt pending
#define INT_STAT_TMR1      0x0002   //  TMR1 has intrpt pending
#define INT_STAT_TMR0      0x0001   //  TMR0 has intrpt pending
//
// These fields apply to the interrupt request register (INT_IREQ),
// the interrupt in-service register (INT_INSV), and the interrupt
// mask register (INT_MASK)
#define INT_SPT0           0x0400   //  serial port
#define INT_WATCHDOG       0x0200   //  watchdog timer (EM/ER)
#define INT_SPT1           0x0200   //  serial port 1 (ES)
#define INT_I4             0x0100   //  INT4
#define INT_I3             0x0080   //  INT3
#define INT_I2             0x0040   //  INT2
#define INT_I1             0x0020   //  INT1
#define INT_I0             0x0010   //  INT0
#define INT_D1             0x0008   //  DMA1
#define INT_D0             0x0004   //  DMA0
#define INT_I6             INT_D1   //  DMA1
#define INT_I5             INT_D0   //  DMA0
#define INT_TIMER          0x0001   //  any timer (see INT_STAT)
// EOI register fields
#define EOI_NONSPEC        0x8000   //  non-specific EOI
// Interrupt poll and poll status register fields
#define INT_POLL_IREQ      0x8000   //  interrupt pending flag
// Synchronous  serial port status register fields (SS_STAT)
#define SS_STAT_ERR        0x0004   //  error flag
#define SS_STAT_COMPLETE   0x0002   //  transaction complete
#define SS_STAT_BUSY       0x0001   //  SS port busy flag
// Synchronous  serial port control register fields (SS_CTL)
#define SS_CTL_CLK2        0x0000   //  SS clck = 1/2 proc clck
#define SS_CTL_CLK4        0x0002   //  SS clck = 1/4 proc clck
#define SS_CTL_CLK8        0x0004   //  SS clck = 1/8 proc clck
#define SS_CTL_CLK16       0x0006   //  SS clck = 1/16proc clck
//
//  -------------------------------------------------------------
//   Auxiliary Configuration Register (offset 0xf2) -- ES ONLY
//  
//   Serial port hardware handshaking bits

#define AUXC_SPRT1_HS1     0x0040   //  1 = ERR, 0 CTS flow control
#define AUXC_SPRT1_HS0     0x0020   //  1 = RTS, 0 RTR flow control
#define AUXC_SPRT0_HS1     0x0010   //  1 = ERR, 0 CTS flow control
#define AUXC_SPRT0_HS0     0x0008   //  1 = RTS, 0 RTR flow control
#define AUXC_SPRT1_ERR     0x0040   //  SPRT1 ERR flow control
#define AUXC_SPRT1_RTS     0x0020   //  SPRT1 RTS flow control
#define AUXC_SPRT0_ERR     0x0010   //  SPRT0 ERR flow control
#define AUXC_SPRT0_RTS     0x0008   //  SPRT0 ERR flow control
#define AUXC_SPRT1_CTS     0x0000   //  SPRT1 CTS flow control
#define AUXC_SPRT1_RTR     0x0000   //  SPRT1 RTR flow control
#define AUXC_SPRT0_CTS     0x0000   //  SPRT0 CTS flow control
#define AUXC_SPRT0_RTR     0x0000   //  SPRT0 RTR flow control

// Static bus sizing configuration bits
#define AUXC_LSIZ          0x0004   //  set to 1 for 8-bit LCS size
#define AUXC_MSIZ          0x0002   //  set to 1 for 8-bit non LCS/non UCS mem size
#define AUXC_IOSZ          0x0001   //  set to 1 for 8-bit IO size
//
//  -------------------------------------------------------------
//  Watchdog timer register defined (0xe6)  -- ES ONLY
#define WDOG_ENA_ES           0x8000
#define WDOG_INT_ES           0x4000
#define WDOG_RSTF_ES          0x2000   
#define WDOG_NMIF_ES          0x1000   
#define WDOG_TMODE_ES         0x0800
#define WDOG_MULT_10X_ES      0x0001
#define WDOG_MULT_20X_ES      0x0002
#define WDOG_MULT_21X_ES      0x0004
#define WDOG_MULT_22X_ES      0x0008
#define WDOG_MULT_23X_ES      0x0010
#define WDOG_MULT_24X_ES      0x0020
#define WDOG_MULT_25X_ES      0x0040
#define WDOG_MULT_26X_ES      0x0080

//  Keys for watchdog timer
#define WDOG_CLR1_ES          0xaaaa
#define WDOG_CLR2_ES          0x5555
#define WDOG_WR1_ES           0x3333
#define WDOG_WR2_ES           0xcccc
//
// ======================================================================
// Interrupt types
// These are the values to write to the EOI register
#define EOITYPE_TMR0       0x08
#define EOITYPE_TMR1       EOITYPE_TMR0
#define EOITYPE_TMR2       EOITYPE_TMR0
#define EOITYPE_DMA0       0x0a
#define EOITYPE_DMA1       0x0b
#define EOITYPE_INT0       0x0c
#define EOITYPE_INT1       0x0d
#define EOITYPE_INT2       0x0e
#define EOITYPE_INT3       0x0f
#define EOITYPE_INT4       0x10
#define EOITYPE_INT5       EOITYPE_DMA0
#define EOITYPE_INT6       EOITYPE_DMA1
#define EOITYPE_SPRT       0x14
#define EOITYPE_SPRT0      0x14
#define EOITYPE_WDOG_EM    0x11            // Watchdog timer on EM/ER
#define EOITYPE_SPRT1      0x11            // Serial port 1 on ES
#define EOITYPE_NONSPEC    0x8000

#define ITYPE_DIV          0x0             //  Divide error
#define ITYPE_TRACE        0x1             //  trace trap
#define ITYPE_NMI          0x2             //  non-maskable interrupt
#define ITYPE_BREAK        0x3             //  breakpoint
#define ITYPE_OVERFLOW     0x4             //  overflow
#define ITYPE_BOUNDS       0x5             //  bound
#define ITYPE_ILLOP        0x6             //  illegal opcode
#define ITYPE_ESC          0x7             //  ESC
#define ITYPE_TMR0         EOITYPE_TMR0    //  Timer 0
#define ITYPE_TMR1         0x12            //  Timer 1
#define ITYPE_TMR2         0x13            //  Timer 2
#define ITYPE_DMA0         EOITYPE_DMA0    //  DMA 0
#define ITYPE_DMA1         EOITYPE_DMA1    //  DMA 1
#define ITYPE_INT0         EOITYPE_INT0    //  INT0
#define ITYPE_INT1         EOITYPE_INT1    //  INT1
#define ITYPE_INT2         EOITYPE_INT2    //  INT2
#define ITYPE_INT3         EOITYPE_INT3    //  INT3
#define ITYPE_INT4         EOITYPE_INT4    //  INT4
#define ITYPE_INT5         EOITYPE_INT5    //  INT5 -- ES only
#define ITYPE_INT6         EOITYPE_INT6    //  INT6 -- ES only
#define ITYPE_SPRT         EOITYPE_SPRT    //  Serial Port 0
#define ITYPE_SPRT0        EOITYPE_SPRT0   //  Serial Port 0
#define ITYPE_SPRT1        EOITYPE_SPRT1   //  Serial Port 1 on ES
#define ITYPE_WDOG_EM      EOITYPE_WDOG_EM //  Watchdog timer on EM/ER
#define ITYPE_WDOG_ES      ITYPE_NMI       //  Watchdog timer on ES


// Define CPU PIO
/*
#define IC_CTRL		0x0001		// PIO0
#define IC_CLKSEL	0x0002		// PIO1
#define	IC_START	0x0004		// PIO2
#define	IC_OFF		0x0008		// PIO3
#define	IC_ALARM	0x0010		// PIO4
#define	FL_CE2		0x0040		// PIO6
#define	MSR_RDD2	0x0400		// PIO10
#define	MSR_RDD3	0x0800		// PIO11
#define	MSR_CPD		0x1000		// PIO12
#define	WDI			0x2000		// PIO13
#define	LCD_BL		0x4000		// PIO14
#define	FL_CE1		0x0010		// PIO20
#define FL_RE		0x0020		// PIO21
#define	FL_ALE		0x0100		// PIO24
#define	FL_WE		0x0200		// PIO25
#define	FL_CLE		0x0400		// PIO26
#define	BUZZER		0x2000		// PIO29
*/
 
#define IC_CTRL		0x0001		// PIO0
#define IC_CLKSEL	0x0002		// PIO1
#define	IC_START	0x0004		// PIO2
#define	IC_OFF		0x0008		// PIO3
#define	IC_ALARM	0x0010		// PIO4
#define	BUZZER		0x0040		// PIO6
#define	MSR_RDD2	0x0400		// PIO10
#define	MSR_RDD3	0x0800		// PIO11
#define	MSR_CPD		0x1000		// PIO12
#define	WDI			0x2000		// PIO13
#define	FL_WP1		0x4000		// PIO14
#define	FL_CE1		0x0010		// PIO20
#define FL_CE2		0x0020		// PIO21
#define	FL_RE 		0x0100		// PIO24
#define	FL_ALE		0x0200		// PIO25
#define	FL_WE		0x0400		// PIO26
#define	FL_CLE 		0x2000		// PIO29

#endif