#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file e:/3/tag_mem\work.tag_mem_tst.prj
#-- Written on Fri Dec 19 12:32:46 2008


#device options
set_option -technology LATTICE-XP2
set_option -part LFXP2_17E
set_option -speed_grade -5

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler true
set_option -resource_sharing true

#use verilog 2001 standard option
set_option -vlog_std v2001

#map options
set_option -frequency 200
set_option -fanout_limit 100
set_option -auto_constrain_io true
set_option -disable_io_insertion false
set_option -retiming false
set_option -pipe false
set_option -force_gsr false
set_option -compiler_compatible true
set_option -dup false

#simulation options
set_option -write_verilog true
set_option -write_vhdl true

#timing analysis options
set_option -num_critical_paths 3
set_option -num_startend_points 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 0

#synplifyPro options.
set_option -fixgatedclocks 3

#synplifyPro options.
set_option -fixgeneratedclocks 3

#-- add_file options
add_file -vhdl -lib work "d:/ispTOOLS7_2/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd"
add_file -verilog -lib work "tag_mem.h"
add_file -vhdl -lib work "tag_mem.vhd"
add_file -vhdl -lib work "tag_mem0.vhd"
add_file -vhdl -lib work "pll0.vhd"
add_file -vhdl -lib work "tag_mem_tst.vhd"

#-- top module name
set_option -top_module work.tag_mem_tst

#-- set result format/file last
project -result_file "tag_mem_tst.edi"

#-- error message log file
project -log_file tag_mem_tst.srf

#-- run Synplify with 'arrange VHDL file'
project -run