/* s3c2410xIntrCtl.c - MagicARM2410 interrupt controller driver */

#include "vxWorks.h"
#include "config.h"

IMPORT	FUNCPTR sysIntLvlVecChkRtn;
IMPORT	FUNCPTR sysIntLvlEnableRtn;
IMPORT	FUNCPTR sysIntLvlDisableRtn;

/* hardware access methods */
#ifndef s3c2410x_INT_REG_READ
#define s3c2410x_INT_REG_READ(reg,result) \
	((result) = *(volatile UINT32 *)(reg))
#endif

#ifndef s3c2410x_INT_REG_WRITE
#define s3c2410x_INT_REG_WRITE(reg,data) \
	(*((volatile UINT32 *)(reg)) = (data))
#endif


/* Current interrupt level setting (s3c2410xIntLvlChg). */

/* 
 * A mask word.  Bits are set in this word when a specific level
 * is enabled. It is used to mask off individual levels that have
 * not been explicitly enabled.
 */
LOCAL UINT32 s3c2410xIntLvlEnabled;


/* forward declarations */
STATUS	s3c2410xIntLvlVecChk (int*, int*);
STATUS	s3c2410xIntLvlEnable (int);
STATUS	s3c2410xIntLvlDisable (int);

/*
 * s3c2410xIntDevInit - initialize the interrupt controller
 *
 * This routine will:
 *	<1> Initialize the interrupt controller device;
 *	<2> Disabling all interrupt sources;
 *	<3> Connect the device driver specific routines into the architecture level hooks.
 *
 *	If the BSP needs to create a wrapper routine around any of the arhitecture level routines,
 *	it should install the pointer to the wrapper routine after calling this routine.
 * 
 * RETURNS: N/A.
 */
int s3c2410xIntDevInit (void)
{
	UINT32 tempUINT32 = 0;
	
	/* <1> Initialize the interrupt controller device; */
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTMSK,0xffffffff);	/* Mask all Interrupt. */
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTSUBMSK,0x7ff);	/* Mask all subInterrupt. */
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_EINTMASK,0x00FFFFF0);	/* Mask all EINT Interrupt. */
	
	s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_SUBSRCPND,tempUINT32);
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_SUBSRCPND,tempUINT32);	/* Clear SUBSRCPND */


	s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_EINTPND,tempUINT32);
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_EINTPND,tempUINT32);	/* Clear EINT EINTPENDn */
	
	s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_SRCPND,tempUINT32);
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_SRCPND,tempUINT32);	/* Clear SRCPND */
	
	s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTPND,tempUINT32);
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTPND,tempUINT32);	/* Clear INTPND. */
	
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTMOD,0);		/* Select IRQ mode. */
	
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_PRIORITY,0);		/* Set priority. */
	
	
	
	/* <3> Install the driver routines in the architecture hooks */
	sysIntLvlVecChkRtn	= s3c2410xIntLvlVecChk;
	sysIntLvlEnableRtn	= s3c2410xIntLvlEnable;
	sysIntLvlDisableRtn	= s3c2410xIntLvlDisable;

	/* all sources disabled */
	s3c2410xIntLvlEnabled = 0;

	return OK;
}

/*
 * s3c2410xIntLvlVecChk - check for and return any pending interrupts
 *
 * This routine interrogates the hardware to determine the highest priority
 * interrupt pending.  It returns the vector associated with that interrupt, and
 * also the interrupt priority level prior to the interrupt (not the
 * level of the interrupt).  The current interrupt priority level is then
 * raised to the level of the current interrupt so that only higher priority
 * interrupts will be accepted until this interrupt is finished.
 *
 * The return value ERROR indicates that no pending interrupt was found and
 * that the level and vector values were not returned.
 *
 * RETURNS: OK or ERROR if no interrupt is pending.
 */
STATUS  s3c2410xIntLvlVecChk
	(
		int* pLevel,  /* ptr to receive old interrupt level */
		int* pVector  /* ptr to receive current interrupt vector */
	)
{
	UINT32 tempUINT32;
	UINT32 int_pand;
	/* Read pending interrupt register and mask undefined bits */
	s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTPND, tempUINT32);

	/* If no interrupt is pending, return ERROR */
	if((tempUINT32 & s3c2410x_INT_CSR_MASK_VAL) == 0) return ERROR;

	/* get the number of the pending interrupt */
	s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTOFFSET, tempUINT32);

	*pVector = tempUINT32;

	 switch(tempUINT32)
	 	{
			case INT_LVL_EINT_0:
				s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTMSK,int_pand);
				s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTMSK, (int_pand|BIT0));
				break;
			case INT_LVL_EINT_1:
				s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTMSK,int_pand);
				s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTMSK, (int_pand|BIT1));
				break;
			case INT_LVL_EINT_2:
				s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTMSK,int_pand);
				s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTMSK, (int_pand|BIT2));
				break;
			case INT_LVL_EINT_3:
				s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTMSK,int_pand);
				s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTMSK, (int_pand|BIT3));
				break;
			case INT_LVL_EINT_4_7:
				s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_EINTMASK,int_pand);
				s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_EINTMASK, (int_pand|0xf0));
				break;
			case INT_LVL_EINT_8_23:
				s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_EINTMASK, 0xfffff0);
				break;			
			case INT_LVL_ADC:
				s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTSUBMSK,int_pand);
				s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTSUBMSK, (int_pand|0x0400));
				break;
			case INT_LVL_RTC:
				s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTMSK,int_pand);
				s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTMSK, (int_pand|BIT30));
				break;
			case INT_LVL_UART_2:
				s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTSUBMSK,int_pand);
				s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTSUBMSK, (int_pand|0x01c0));
				break;
			case INT_LVL_UART_1:
				s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTSUBMSK,int_pand);
				s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTSUBMSK, (int_pand|0x0038));
				break;
			case INT_LVL_UART_0:
				s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTSUBMSK,int_pand);
				s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTSUBMSK, (int_pand|0x0007));
				break;
			case INT_LVL_LCD:/*add by supercontrol for lcd*/
			  s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTMSK,int_pand);
			  s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTMSK, (int_pand|BIT16));
			case INT_LVL_IIC:/*add by supercontrol for iic*/
				s3c2410x_INT_REG_READ(s3c2410x_INT_CSR_INTMSK,int_pand);
			  s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTMSK, (int_pand|BIT27));
			  break;
			default:
	 	}
	/* s3c2410xIntLvlDisable(tempUINT32); */
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_SRCPND, (1<<tempUINT32));
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTPND, (1<<tempUINT32));

	return OK;
}


/*
 * s3c2410xIntLvlEnable - enable a single interrupt level
 *
 * Enable a specific interrupt level.  The enabled level will be allowed to
 * generate an interrupt, when the overall interrupt level is set below the
 * specified level.  Without being enabled, the interrupt is blocked regardless
 * of the overall interrupt level setting.
 *
 * RETURNS: OK or ERROR if the specified level cannot be enabled.
 */
STATUS  s3c2410xIntLvlEnable
	(
		int level  /* level to be enabled */
	)
{
	int key;

	if(level < 0 || level >= s3c2410x_INT_NUM_LEVELS) return ERROR;
	/* set bit in enable mask */
	key = intLock();
	s3c2410xIntLvlEnabled |= (1 << (level));
	
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTMSK,	((~s3c2410xIntLvlEnabled) & s3c2410x_INT_CSR_MASK_VAL));
	intUnlock(key);
	
	return OK;
}

/*
 * s3c2410xIntLvlDisable - disable a single interrupt level
 *
 * Disable a specific interrupt level.  The disabled level is prevented
 * from generating an interrupt even if the overall interrupt level is set
 * below the specified level.
 *
 * RETURNS: OK or ERROR, if the specified interrupt level cannot be disabled.
 */
STATUS  s3c2410xIntLvlDisable
	(
		int level  /* level to be disabled */
	)
{
	int key;
	
	if(level < 0 || level >= s3c2410x_INT_NUM_LEVELS) return ERROR;
	/* clear bit in enable mask */
	key = intLock();
	s3c2410xIntLvlEnabled &= ~(1 <<( level));
	s3c2410x_INT_REG_WRITE(s3c2410x_INT_CSR_INTMSK,	((~s3c2410xIntLvlEnabled) & s3c2410x_INT_CSR_MASK_VAL));
	intUnlock(key);

	return OK;
}