/* romInit.s - MagicARM2410 ROM initialization module *//*DESCRIPTION	The entry code for VxWorks images that start running from ROM	Such as 'bootrom' and 'vxWorks_rom'.	The entry point romInit() is the first code executed on power-up.		romInit() performs the minimal setup needed to\	 call the generic C routine romStart() with parameter BOOT_COLD.romInit() 	masks interrupts:		processor		interrupt controller	sets the initial stack pointer:		to STACK_ADRS which is defined in configAll.h .		Other hardware and device initialisation is performed later in the sysHwInit routine in sysLib.c.sysToMonitor()	jumps to a location after the beginning of romInit,	 (defined by ROM_WARM_ADRS) to perform a "warm boot".	 This entry point allows a parameter to be passed to romStart().The routines in this module don't use the "C" frame pointer %r11@ ! orestablish a stack frame.*//* * Behaviours: *		Save boot type; *		Turn off the watchdog; *		Take a delay for cold boot; *		Set MMU Control Register; *		Disable interrupts; *		Set system clock; *		Initialize memory; *		r1 now contains memory size: store this in Memory_Size variable; *		Initialize stack pointer; *		jump to C entry point in ROM; */#define	_ASMLANGUAGE#include "vxWorks.h"#include "sysLib.h"#include "asm.h"#include "regs.h"	#include "config.h"#include "arch/arm/mmuArmLib.h"        .data        .globl   VAR(copyright_wind_river)        .long    VAR(copyright_wind_river)/* internals */	.globl	FUNC(romInit)		/* start of system code */	.globl	VAR(sdata)		/* start of data */        .globl  _sdata	.globl	VAR(s3c2410xMemSize)	/* actual memory size *//* externals */	.extern	FUNC(romStart)	/* system initialization routine */_sdata:VAR_LABEL(sdata)	.asciz	"start of data"	.balign	4/* variables */	.dataVAR_LABEL(s3c2410xMemSize)	.long	0	.text	.balign 4/********************************************************************************* romInit - entry point for VxWorks in ROM** romInit*     (*     int startType	/@ only used by 2nd entry point @/*     )* INTERNAL* sysToMonitor examines the ROM for the first instruction and the string* "Copy" in the third word so if this changes, sysToMonitor must be updated.*/_ARM_FUNCTION(romInit)_romInit:cold:	mov	r0, #BOOT_COLD	/* fall through to warm boot entry */warm:	b	start	b	Swi	b	Pabort	b	Dabort	b	cold	b	Irq	b	Fiq	Swi:	sub	sp,sp,#4	stmfd	sp!,{r1}	ldr     r1,vecSwi	str     r1,[sp,#4]	ldmfd   sp!,{r1,pc}vecSwi:	.long 0x30000008 /*VEC_BASE_ADRS+0X08*/	Pabort:	sub	sp,sp,#4	stmfd	sp!,{r1}	ldr     r1,vecPabort	str     r1,[sp,#4]	ldmfd   sp!,{r1,pc}vecPabort:	.long 0x3000000c /*VEC_BASE_ADRS+0X0c*/Dabort:	sub	sp,sp,#4	stmfd	sp!,{r1}	ldr     r1,vecDabort	str     r1,[sp,#4]	ldmfd   sp!,{r1,pc}vecDabort:	.long 0x30000010 /*VEC_BASE_ADRS+0X10*/	Irq:	sub	sp,sp,#4	stmfd	sp!,{r1}	ldr     r1,vecIrq	str     r1,[sp,#4]	ldmfd   sp!,{r1,pc}vecIrq:	.long 0x30000018 /*VEC_BASE_ADRS+0X18*/Fiq:	sub	sp,sp,#4	stmfd	sp!,{r1}	ldr     r1,vecFiq	str     r1,[sp,#4]	ldmfd   sp!,{r1,pc}vecFiq:	.long 0x3000001c /*VEC_BASE_ADRS+0X1c*/		/* copyright notice appears at beginning of ROM (in TEXT segment) */	.ascii   "Copyright 2008 supercontrol"	.ascii   "\nCopyright 2008 supercontrol"	.balign 4start:/* Turn off the watchdog. */		ldr	r1, =rWTCON_ADR		/* r0->WTCON */	ldr	r2, =rWTCON_INIT_VALUE	/* r1 = WTCON's initValue */	str	r2, [r1]		/* Turn off the watch-dog *//* Take a delay for cold boot. */	teqs	r0, #BOOT_COLD	moveq	r1, #____BOOT_DELAY_VALUE	movne	r1, #1delay_loop:	subs	r1, r1, #1	bne	delay_loop	/*	 * Set processor and MMU to known state as follows (we may have not	 * been entered from a reset). We must do this before setting the CPU	 * mode as we must set PROG32/DATA32.	 *	 * MMU Control Register layout.	 *	 * bit	 *  0 M 0 MMU disabled	 *  1 A 0 Address alignment fault disabled, initially	 *  2 C 0 Data cache disabled	 *  3 W 0 Write Buffer disabled	 *  4 P 1 PROG32	 *  5 D 1 DATA32	 *  6 L 1 Should Be One (Late abort on earlier CPUs)	 *  7 B ? Endianness (1 => big)	 *  8 S 0 System bit to zero } Modifies MMU protections, not really	 *  9 R 1 ROM bit to one     } relevant until MMU switched on later.	 * 10 F 0 Should Be Zero	 * 11 Z 0 Should Be Zero (Branch prediction control on 810)	 * 12 I 0 Instruction cache control	 *//* Setup MMU Control Register */	mov	r1, #MMU_INIT_VALUE		/* Defined in mmuArmLib.h */#if defined(INTEGRATOR_EARLY_I_CACHE_ENABLE)	orr	r1, r1, #MMUCR_I_ENABLE		/* conditionally enable Icache*/#endif	mcr	p15, 0, r1, c1, c0, 0	/* Write to MMU CR */	/*	 * If MMU was on before this, then we'd better hope it was set	 * up for flat translation or there will be problems. The next	 * 2/3 instructions will be fetched "translated" (number depends	 * on CPU).	 *	 * We would like to discard the contents of the Write-Buffer	 * altogether, but there is no facility to do this. Failing that,	 * we do not want any pending writes to happen at a later stage,	 * so drain the Write-Buffer, i.e. force any pending writes to	 * happen now.	 */	/* drain write-buffer */	mov	r1, #0				/* data SBZ */	mcr	p15, 0, r1, c7, c10, 4	/* Flush (invalidate) both I and D caches */	mcr	p15, 0, r1, c7, c7, 0	/* R1 = 0 from above, data SBZ*/        /*	 * Set Process ID Register to zero, this effectively disables	 * the process ID remapping feature.	 */	mov	r1, #0	mcr	p15, 0, r1, c13, c0, 0/* Disable CPU interrupts and individual interrupts in the interrupt controller. */	mrs	r1, cpsr	bic	r1, r1, #MASK_MODE	orr	r1, r1, #(MODE_SVC32 | IRQ_ENABLE_Bit | FIQ_ENABLE_Bit)	msr	cpsr, r1	ldr	r1, =0xffffffff	ldr	r2, =rINTMSK_ADR		/* R2->interrupt mask registor of controller */	str	r1, [r2]			/* disable all sources */	ldr	r2, =rINTSUBMSK_ADR		/* R2->sub-interrupt mask registor of controller */	str	r1, [r2]			/* disable all sub-sources */	/*	 * Jump to the normal (higher) ROM Position. After a reset, the	 * ROM is mapped into memory from* location zero upwards as well	 * as in its normal position at This code could be executing in	 * the lower position. We wish to be executing the code, still	 * in ROM, but in its normal (higher) position before we remap	 * the machine so that the ROM is no longer dual-mapped from zero	 * upwards, but so that RAM appears from 0 upwards.	 */	ldr	pc, L$_HiPosnHiPosn:	/*	 * We are now executing in the normal (higher, still in ROM)	 * position in the memory map.  Remap memory to post-reset state,	 * so that the ROM is not now dual-mapped to zero upwards, but	 * RAM is mapped from zero, instead.	 */	/* phoenix_remap */	/*	MOV	r1, #INTEGRATOR_HDR_REMAP	MOV	r2, #INTEGRATOR_HDR_BASE	STR	r1, [r2, #INTEGRATOR_HDR_CTRL_OFFSET]	*/		/* Set system clock.*/		/* set the MMU control register asynchronous mode. */	mrc	p15, 0, r2, c1, c0, 0	orr	r2, r2, #MMUCR_ASYNC	mcr	p15, 0, r2, c1, c0, 0	/* Set PLL lock time. */	ldr	r2, =rLOCKTIME_ADR	ldr	r1, =rLOCKTIME_INIT_VALUE	str	r1, [r2]		/* Set FCLK:HCLK:PCLK = 1:2:4 */	ldr	r2, =rCLKDIVN_ADR	ldr	r1, =rCLKDIVN_INIT_VALUE	str	r1, [r2]		/* Set FCLK = 200MHz by Fosc = 12MHz */	ldr	r2, =rMPLLCON_ADR	ldr	r1, =rMPLLCON_INIT_VALUE	/* 	ldr	r1, =0x5c040 */	str	r1, [r2]		/* Set clock control register */	ldr	r2, =rCLKCON_ADR	ldr	r1, =rCLKCON_INIT_VALUE	str	r1, [r2]		/* Set clock slow register */	ldr	r2, =rCLKSLOW_ADR	ldr	r1, =rCLKSLOW_INIT_VALUE	str	r1, [r2]/* Initialize memory . */	/* Set bus width for each bank, 0x22111112 */	ldr	r2, =rBWSCON_ADR	ldr	r1, =rBWSCON_INIT_VALUE	str	r1, [r2]		/* Set bank0 and bank5 , 0x00000700 */	ldr	r2, =rBANKCON0_ADR	ldr	r1, =rBANKCON0_INIT_VALUE	str	r1, [r2]	ldr	r2, =rBANKCON3_ADR	ldr	r1, =rBANKCON3_INIT_VALUE	str	r1, [r2]		/* Set bank6 for SDRAM, 0x00018000 */	ldr	r2, =rBANKCON6_ADR	ldr	r1, =rBANKCON6_INIT_VALUE	str	r1, [r2]	/* Set refresh for SDRAM, 0x00860459 */	ldr	r2, =rREFRESH_ADR	ldr	r1, =rREFRESH_INIT_VALUE	str	r1, [r2]		/* Set bank size for SDRAM, 0x000000b7 */	ldr	r2, =rBANKSIZE_ADR	ldr	r1, =rBANKSIZE_INIT_VALUE	str	r1, [r2]		/* Set bank mode, 0x00000030 */	ldr	r2, =rMRSRB6_ADR	ldr	r1, =rMRSRB6_INIT_VALUE	str	r1, [r2]	/* r1 now contains memory size: store this in Memory_Size variable */		ldr	r1, =SZ_64M	ldr	r3, L$_memSize	str	r1, [r3]	mov	r3, r1		/* Need to return size in both these registers*//*GPIO CONFIG*/	/**PORT A*Ports :GPA22 GPA21   GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12*Signal:nFCE  nRSTOUT nFRE  ALE   CLE   nGCS5 nGCS4 nGCS3 nGCS2 nGCS1*Ports :GPA11 GPA10   GPA9   GPA8   GPA7   GPA6   GPA5   GPA4   GPA3   GPA2   GPA1   GPA0*Signal:ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0*/  LDR r0,=rGPACON  LDR r1,=0x7fffff  STR r1,[r0]/**PORT B*Ports  :GPB10   GPB9    GPB8    GPB7    GPB6    GPB5     GPB4    GPB3   GPB2   GPB1       GPB0*Signal :nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard*Setting:INPUT   OUTPUT  INPUT   OUTPUT  INPUT   OUTPUT   OUTPUT  OUTPUT OUTPUT OUTPUT     OUTPUT*/  LDR r0,=rGPBCON  LDR r1,=0x044555  STR r1,[r0]  LDR r0,=rGPBUP  LDR r1,=0x7ff  STR r1,[r0]/**PORT C*Ports  :GPC15  GPC14  GPC13  GPC12  GPC11  GPC10  GPC9  GPC8  GPC7   GPC6   GPC5   GPC4  GPC3   GPC2  GPC1  GPC0*Signal :VD7    VD6    VD5    VD4    VD3    VD2    VD1   VD0   LCDVF2 LCDVF1 LCDVF0 VM    VFRAME VLINE VCLK  LEND*/  LDR r0,=rGPCCON  LDR r1,=0xaaaaaaaa  STR r1,[r0]  LDR r0,=rGPCUP  LDR r1,=0xffff  STR r1,[r0]/**PORT D*Ports  :GPD15  GPD14  GPD13  GPD12  GPD11  GPD10  GPD9  GPD8  GPD7   GPD6   GPD5   GPD4  GPD3   GPD2  GPD1  GPD0*Signal :VD23   VD22   VD21   VD20   VD19   VD18   VD17  VD16  VD15   VD14   VD13   VD12  VD11   VD10  VD9   VD8*/  LDR r0,=rGPDCON  LDR r1,=0xaaaaaaaa  STR r1,[r0]  LDR r0,=rGPDUP  LDR r1,=0xffff  STR r1,[r0]/**PORT E*Ports  :GPF15  GPF14  GPF13  GPF12   GPF11   GPF10   GPF9    GPF8    GPF7    GPF6   GPF5   GPF4*Signal :IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD  SDCLK  I2SSD0*/  LDR r0,=rGPECON  LDR r1,=0xaaaaaaaa  STR r1,[r0]  LDR r0,=rGPEUP  LDR r1,=0xffff  STR r1,[r0]/**PORT F*Ports  :GPF7    GPF6    GPF5    GPF4    GPF3        GPF2   GPF1    GPF0*Signal :nLED_8  nLED_4  nLED_2  nLED_1  nIRQ_PCMCIA EINT2  KBDINT  EINT0*Setting:OUTPUT  OUTPUT  OUTPUT  EINT4   EINT3       EINT2  EINT1   EINT0*/  LDR r0,=rGPFCON  LDR r1,=0xaaaa  STR r1,[r0]  LDR r0,=rGPFUP  LDR r1,=0xff  STR r1,[r0]/**PORT G*Ports  :GPG15  GPG14  GPG13  GPG12  GPG11   GPG10    GPG9     GPG8     GPG7      GPG6*Signal :nYPON  YMON   nXPON  XMON   EINT19  DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI*Setting:nYPON  YMON   nXPON  XMON   EINT19  OUTPUT   OUTPUT   OUTPUT   SPICLK1   SPIMOSI1*Ports  :GPG5       GPG4      GPG3   GPG2    GPG1    GPG0*Signal :KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA*Setting:SPIMISO1   LCD_PWREN EINT11 nSS0    EINT9   EINT82007.9.12 GPG8 change to EINT16 for LCD interrupt*/  LDR r0,=rGPGCON/*LDR r1,=0xff95ff9a  change by supercontrol for EINT16*/  LDR r1,=0xff96ff9a  STR r1,[r0]  LDR r0,=rGPGUP  LDR r1,=0xffff  STR r1,[r0]/**PORT H*Ports  :GPH10   GPH9    GPH8  GPH7   GPH6   GPH5   GPH4  GPH3   GPH2  GPH1  GPH0*Signal :CLKOUT1 CLKOUT0 UCLK  nCTS1  nRTS1  RXD1   TXD1  RXD0   TXD0  nRTS0 nCTS0*Binary :10      10      11    11     10     10     10    10     10    10    10*/  LDR r0,=rGPHCON  LDR r1,=0x2afaaa  STR r1,[r0]  LDR r0,=rGPHUP  LDR r1,=0x7ff  STR r1,[r0]/*EXTERNAL INTR SET*/  LDR r0,=rEXTINT0  LDR r1,=0x44444444  STR r1,[r0]  LDR r0,=rEXTINT1  LDR r1,=0x22222222  STR r1,[r0]  LDR r0,=rEXTINT2  LDR r1,=0x22222222  STR r1,[r0]	/* Initialize the stack pointer to just before where the uncompress code,  * copied from ROM to RAM, will run. */	ldr	sp, L$_STACK_ADDR	mov	fp, #0			/* zero frame pointer *//* jump to C entry point in ROM: routine - entry point + ROM base */#if	(ARM_THUMB)	ldr	r12, L$_rStrtInRom	orr	r12, r12, #1		/* force Thumb state */	bx	r12#else	ldr	pc, L$_rStrtInRom#endif	/* (ARM_THUMB) *//******************************************************************************//* * PC-relative-addressable pointers - LDR Rn,=sym is broken * note "_" after "$" to stop preprocessor performing substitution */	.balign	4L$_HiPosn:	.long	ROM_TEXT_ADRS + HiPosn - FUNC(romInit)L$_rStrtInRom:	.long	ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)L$_STACK_ADDR:	.long	STACK_ADRSL$_memSize:	.long	VAR(s3c2410xMemSize)/*________RESET_ADR:	b	cold	 reset................0x00000000 *//*________UND_ADR:	nop		 unknown ins..........0x00000004 *//*________SWI_ADR:	nop		 software.............0x00000008 *//*________IABT_ADR:	nop		 instruction abort....0x0000000c *//*________DABT_ADR:	nop		 data abort...........0x00000010 *//*			nop		 reserved.............0x00000014 *//*________IRQ_ADR:	nop		 IRQ..................0x00000018 *//*________FIQ_ADR:	nop		 FIQ..................0x0000001c */