?? zhuangtaiji.sim.rpt
字號:
; |zhuangtaiji|State~22 ; |zhuangtaiji|State~22 ; out ;
; |zhuangtaiji|qc~0 ; |zhuangtaiji|qc~0 ; out ;
; |zhuangtaiji|qc~1 ; |zhuangtaiji|qc~1 ; out ;
; |zhuangtaiji|process0~6 ; |zhuangtaiji|process0~6 ; out0 ;
; |zhuangtaiji|State~23 ; |zhuangtaiji|State~23 ; out ;
; |zhuangtaiji|State~24 ; |zhuangtaiji|State~24 ; out ;
; |zhuangtaiji|State~25 ; |zhuangtaiji|State~25 ; out ;
; |zhuangtaiji|State~26 ; |zhuangtaiji|State~26 ; out ;
; |zhuangtaiji|State~27 ; |zhuangtaiji|State~27 ; out ;
; |zhuangtaiji|State~28 ; |zhuangtaiji|State~28 ; out ;
; |zhuangtaiji|qd~0 ; |zhuangtaiji|qd~0 ; out ;
; |zhuangtaiji|qd~1 ; |zhuangtaiji|qd~1 ; out ;
; |zhuangtaiji|qb~2 ; |zhuangtaiji|qb~2 ; out ;
; |zhuangtaiji|qc~2 ; |zhuangtaiji|qc~2 ; out ;
; |zhuangtaiji|qd~2 ; |zhuangtaiji|qd~2 ; out ;
; |zhuangtaiji|qa~2 ; |zhuangtaiji|qa~2 ; out ;
; |zhuangtaiji|State.s1 ; |zhuangtaiji|State.s1 ; out ;
; |zhuangtaiji|State.s2 ; |zhuangtaiji|State.s2 ; out ;
; |zhuangtaiji|State.s3 ; |zhuangtaiji|State.s3 ; out ;
; |zhuangtaiji|State.s4 ; |zhuangtaiji|State.s4 ; out ;
; |zhuangtaiji|z0~reg0 ; |zhuangtaiji|z0~reg0 ; out ;
; |zhuangtaiji|z1~reg0 ; |zhuangtaiji|z1~reg0 ; out ;
; |zhuangtaiji|z2~reg0 ; |zhuangtaiji|z2~reg0 ; out ;
; |zhuangtaiji|z3~reg0 ; |zhuangtaiji|z3~reg0 ; out ;
; |zhuangtaiji|z4~reg0 ; |zhuangtaiji|z4~reg0 ; out ;
; |zhuangtaiji|qb ; |zhuangtaiji|qb ; out ;
; |zhuangtaiji|qc ; |zhuangtaiji|qc ; out ;
; |zhuangtaiji|qd ; |zhuangtaiji|qd ; out ;
; |zhuangtaiji|qa ; |zhuangtaiji|qa ; out ;
; |zhuangtaiji|State.s0 ; |zhuangtaiji|State.s0 ; out ;
; |zhuangtaiji|Clk ; |zhuangtaiji|Clk ; out ;
; |zhuangtaiji|clr ; |zhuangtaiji|clr ; out ;
; |zhuangtaiji|kb0 ; |zhuangtaiji|kb0 ; out ;
; |zhuangtaiji|kb1 ; |zhuangtaiji|kb1 ; out ;
; |zhuangtaiji|kb2 ; |zhuangtaiji|kb2 ; out ;
; |zhuangtaiji|kb3 ; |zhuangtaiji|kb3 ; out ;
; |zhuangtaiji|z0 ; |zhuangtaiji|z0 ; pin_out ;
; |zhuangtaiji|z1 ; |zhuangtaiji|z1 ; pin_out ;
; |zhuangtaiji|z2 ; |zhuangtaiji|z2 ; pin_out ;
; |zhuangtaiji|z3 ; |zhuangtaiji|z3 ; pin_out ;
; |zhuangtaiji|z4 ; |zhuangtaiji|z4 ; pin_out ;
; |zhuangtaiji|State~29 ; |zhuangtaiji|State~29 ; out0 ;
; |zhuangtaiji|State~30 ; |zhuangtaiji|State~30 ; out0 ;
; |zhuangtaiji|Select~35 ; |zhuangtaiji|Select~35 ; out0 ;
; |zhuangtaiji|Select~40 ; |zhuangtaiji|Select~40 ; out0 ;
; |zhuangtaiji|Select~41 ; |zhuangtaiji|Select~41 ; out0 ;
; |zhuangtaiji|Select~45 ; |zhuangtaiji|Select~45 ; out0 ;
; |zhuangtaiji|Select~46 ; |zhuangtaiji|Select~46 ; out0 ;
; |zhuangtaiji|Select~47 ; |zhuangtaiji|Select~47 ; out0 ;
; |zhuangtaiji|Select~50 ; |zhuangtaiji|Select~50 ; out0 ;
; |zhuangtaiji|Select~51 ; |zhuangtaiji|Select~51 ; out0 ;
; |zhuangtaiji|Select~53 ; |zhuangtaiji|Select~53 ; out0 ;
; |zhuangtaiji|Select~55 ; |zhuangtaiji|Select~55 ; out0 ;
; |zhuangtaiji|Select~56 ; |zhuangtaiji|Select~56 ; out0 ;
; |zhuangtaiji|Select~59 ; |zhuangtaiji|Select~59 ; out0 ;
; |zhuangtaiji|Select~60 ; |zhuangtaiji|Select~60 ; out0 ;
+-------------------------+-------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+------------------------+------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+------------------------+------------------------+------------------+
; |zhuangtaiji|Select~36 ; |zhuangtaiji|Select~36 ; out0 ;
; |zhuangtaiji|Select~37 ; |zhuangtaiji|Select~37 ; out0 ;
; |zhuangtaiji|Select~38 ; |zhuangtaiji|Select~38 ; out0 ;
; |zhuangtaiji|Select~39 ; |zhuangtaiji|Select~39 ; out0 ;
; |zhuangtaiji|Select~42 ; |zhuangtaiji|Select~42 ; out0 ;
; |zhuangtaiji|Select~43 ; |zhuangtaiji|Select~43 ; out0 ;
; |zhuangtaiji|Select~44 ; |zhuangtaiji|Select~44 ; out0 ;
; |zhuangtaiji|Select~48 ; |zhuangtaiji|Select~48 ; out0 ;
; |zhuangtaiji|Select~49 ; |zhuangtaiji|Select~49 ; out0 ;
; |zhuangtaiji|Select~52 ; |zhuangtaiji|Select~52 ; out0 ;
; |zhuangtaiji|Select~54 ; |zhuangtaiji|Select~54 ; out0 ;
; |zhuangtaiji|Select~57 ; |zhuangtaiji|Select~57 ; out0 ;
; |zhuangtaiji|Select~58 ; |zhuangtaiji|Select~58 ; out0 ;
; |zhuangtaiji|Select~61 ; |zhuangtaiji|Select~61 ; out0 ;
; |zhuangtaiji|Select~62 ; |zhuangtaiji|Select~62 ; out0 ;
; |zhuangtaiji|Select~63 ; |zhuangtaiji|Select~63 ; out0 ;
+------------------------+------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+------------------------+------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+------------------------+------------------------+------------------+
; |zhuangtaiji|Select~36 ; |zhuangtaiji|Select~36 ; out0 ;
; |zhuangtaiji|Select~37 ; |zhuangtaiji|Select~37 ; out0 ;
; |zhuangtaiji|Select~38 ; |zhuangtaiji|Select~38 ; out0 ;
; |zhuangtaiji|Select~39 ; |zhuangtaiji|Select~39 ; out0 ;
; |zhuangtaiji|Select~42 ; |zhuangtaiji|Select~42 ; out0 ;
; |zhuangtaiji|Select~43 ; |zhuangtaiji|Select~43 ; out0 ;
; |zhuangtaiji|Select~44 ; |zhuangtaiji|Select~44 ; out0 ;
; |zhuangtaiji|Select~48 ; |zhuangtaiji|Select~48 ; out0 ;
; |zhuangtaiji|Select~49 ; |zhuangtaiji|Select~49 ; out0 ;
; |zhuangtaiji|Select~52 ; |zhuangtaiji|Select~52 ; out0 ;
; |zhuangtaiji|Select~54 ; |zhuangtaiji|Select~54 ; out0 ;
; |zhuangtaiji|Select~57 ; |zhuangtaiji|Select~57 ; out0 ;
; |zhuangtaiji|Select~58 ; |zhuangtaiji|Select~58 ; out0 ;
; |zhuangtaiji|Select~61 ; |zhuangtaiji|Select~61 ; out0 ;
; |zhuangtaiji|Select~62 ; |zhuangtaiji|Select~62 ; out0 ;
; |zhuangtaiji|Select~63 ; |zhuangtaiji|Select~63 ; out0 ;
+------------------------+------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Sat Dec 20 15:14:59 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off zhuangtaiji -c zhuangtaiji
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Warning: Found clock-sensitive change during active clock edge at time 55.0 ns on register "|zhuangtaiji|qb"
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 84.62 %
Info: Number of transitions in simulation is 2406
Info: Quartus II Simulator was successful. 0 errors, 1 warning
Info: Processing ended: Sat Dec 20 15:15:00 2008
Info: Elapsed time: 00:00:01
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