?? zhuangtaiji.tan.rpt
字號:
Timing Analyzer report for zhuangtaiji
Sat Dec 20 15:38:41 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'Clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+---------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+---------+----------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 8.200 ns ; kb2 ; qc ; -- ; Clk ; 0 ;
; Worst-case tco ; N/A ; None ; 13.900 ns ; z3~reg0 ; z3 ; Clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 0.600 ns ; kb2 ; State.s4 ; -- ; Clk ; 0 ;
; Clock Setup: 'Clk' ; N/A ; None ; 120.48 MHz ( period = 8.300 ns ) ; qb ; State.s1 ; Clk ; Clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+---------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPF10K10TC144-4 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Clk' ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 120.48 MHz ( period = 8.300 ns ) ; qd ; State.s3 ; Clk ; Clk ; None ; None ; 4.700 ns ;
; N/A ; 120.48 MHz ( period = 8.300 ns ) ; qc ; State.s2 ; Clk ; Clk ; None ; None ; 4.700 ns ;
; N/A ; 120.48 MHz ( period = 8.300 ns ) ; qb ; State.s1 ; Clk ; Clk ; None ; None ; 4.700 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s3 ; State.s3 ; Clk ; Clk ; None ; None ; 4.200 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s2 ; State.s2 ; Clk ; Clk ; None ; None ; 4.200 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s1 ; State.s1 ; Clk ; Clk ; None ; None ; 4.200 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s2 ; State.s3 ; Clk ; Clk ; None ; None ; 3.900 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; qc ; State.s3 ; Clk ; Clk ; None ; None ; 3.900 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s0 ; State.s1 ; Clk ; Clk ; None ; None ; 3.900 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; qa ; State.s1 ; Clk ; Clk ; None ; None ; 3.900 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s3 ; qd ; Clk ; Clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s2 ; qc ; Clk ; Clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s1 ; qb ; Clk ; Clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s0 ; qa ; Clk ; Clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; qa ; qa ; Clk ; Clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s3 ; State.s4 ; Clk ; Clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; qd ; State.s4 ; Clk ; Clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s1 ; State.s2 ; Clk ; Clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; qb ; State.s2 ; Clk ; Clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s0 ; State.s0 ; Clk ; Clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; qd ; qd ; Clk ; Clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; qc ; qc ; Clk ; Clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; qb ; qb ; Clk ; Clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s4 ; State.s4 ; Clk ; Clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s4 ; z4~reg0 ; Clk ; Clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s3 ; z3~reg0 ; Clk ; Clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s2 ; z2~reg0 ; Clk ; Clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s1 ; z1~reg0 ; Clk ; Clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; qa ; State.s0 ; Clk ; Clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; State.s0 ; z0~reg0 ; Clk ; Clk ; None ; None ; 1.800 ns ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+----------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+----------+----------+
; N/A ; None ; 8.200 ns ; kb2 ; qb ; Clk ;
; N/A ; None ; 8.200 ns ; kb2 ; qc ; Clk ;
; N/A ; None ; 8.000 ns ; kb1 ; qb ; Clk ;
; N/A ; None ; 8.000 ns ; kb1 ; qc ; Clk ;
; N/A ; None ; 8.000 ns ; kb3 ; qb ; Clk ;
; N/A ; None ; 8.000 ns ; kb3 ; qc ; Clk ;
; N/A ; None ; 7.700 ns ; kb2 ; qa ; Clk ;
; N/A ; None ; 7.500 ns ; kb0 ; qb ; Clk ;
; N/A ; None ; 7.500 ns ; kb0 ; qc ; Clk ;
; N/A ; None ; 7.500 ns ; kb1 ; qa ; Clk ;
; N/A ; None ; 7.500 ns ; kb3 ; qa ; Clk ;
; N/A ; None ; 7.000 ns ; kb0 ; qa ; Clk ;
; N/A ; None ; 6.900 ns ; clr ; z1~reg0 ; Clk ;
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