module actree(ST,clk,clf,out);
  
input [7:0]ST;
input clk,clf;
output[31:0] out;

reg[31:0] out;
reg[12:0] current_state,next_state; 



//difine state 
parameter          ST0=13'b0000000001000;
parameter          ST1=13'b0000000010000;
parameter          ST2=13'b0000000100000;
parameter          ST3=13'b0000001000000;
parameter          ST4=13'b0000010000000;
parameter          ST5=13'b0000100000001;
parameter          ST6=13'b0001000000000;
parameter          ST7=13'b0010000000010;
parameter          ST8=13'b0100000000000;
parameter          ST9=13'b1000000000100;
parameter          ram0=32'b00000000000000000000000000000000;
parameter          ram1=32'b00000000010100110100100001000101;
parameter          ram2=32'b00000000010010000100100101010011;
parameter          ram3=32'b01001000010001010101001001010011;

//initial the first state
always @(posedge clk or negedge clf)
      if (!clf) 
        current_state<=ST0;
      else 
      current_state<=next_state;
      
always @(current_state or ST)
  begin
     next_state<=ST0;
    case(current_state[2:0])
       001:  out=ram1;
       010:  out=ram2;
       100:  out=ram3;
       default : out=ram0;
     endcase
   
      
  case(current_state)
 ST0: if (ST==8'b01001000)//  H
          next_state<=ST1;
      else 
          if (ST==8'b01010011)//S
              next_state<=ST3;
          else next_state<=ST0;
          
  ST1: if (ST==8'b01000101) //E
          next_state<=ST2;
       else 
          if (ST==8'b01001001)//I
              next_state<=ST6;
          else
             if (ST==8'b01010011)//s
                 next_state<=ST3;
                else
                  if (ST==8'b01001000)//  H
                      next_state<=ST1;
                  else  
                    next_state<=ST0;
          
  ST2: if (ST==8'b01010010) //R
          next_state<=ST8;
       else 
          if (ST==8'b01001000)//  H
              next_state<=ST1;
          else 
            if (ST==8'b01010011)//S
                next_state<=ST3;
            else next_state<=ST0;
       
  ST3: if (ST==8'b01001000)//H
          next_state<=ST4;
       else 
          if (ST==8'b01010011)//S
              next_state<=ST3;
          else next_state<=ST0;
          
  ST4: if (ST==8'b01000101)//E
          next_state<=ST5;
       else 
          if (ST==8'b01001001)//I
              next_state<=ST6;
          else 
              if (ST==8'b01001000)//  H
                  next_state<=ST1;
              else 
              if (ST==8'b01010011)//S
                  next_state<=ST3;
              else next_state<=ST0;
 
  ST5:           
       begin 
        if (ST==8'b01010010)//R
           next_state<=ST8;
        else if (ST==8'b01001000)//H
                next_state<=ST1;
             else if (ST==8'b01010011)//S
                      next_state<=ST3;
                  else 
                      next_state<=ST0;
                 
          end
 
  ST6: if (ST==8'b01010011)//S
          next_state<=ST7;
       else 
          if (ST==8'b01001000)//  H
          next_state<=ST1;
          else    
          next_state<=ST0;

  ST7:  
       if (ST==8'b01001000)//h
           next_state<=ST4;
       else 
          if (ST==8'b01010011)//S
              next_state<=ST3;
          else next_state<=ST0;
        
  ST8: if (ST==8'b01010011)//S
          next_state<=ST9;
       else 
          if (ST==8'b01001000)//  H
          next_state<=ST1;
          else next_state<=ST0;
  
  ST9:  
       if (ST==8'b01001000)//h
           next_state<=ST4;
       else 
          if (ST==8'b01010011)//S
              next_state<=ST3;
          else next_state<=ST0;
  default : next_state<=ST0;
  
  endcase
  
      
  end
  
  endmodule