?? gpsnavidatagen_4ch.v
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`timescale 1ns/1ns //`define DEBUG_NAVI`include "include.v" //generate signals in one satellite, not including navigation bits module GPSDataGenSAT_4ch(in_clk, in_Resetn, out_GPSData, o_NBPulse, sel, a, d, csn, wrn, oen); input in_clk; input in_Resetn; output [2:0] out_GPSData; output o_NBPulse; input sel; input [7:0]a; input csn; input wrn; input oen; inout [31:0]d; parameter SAMPCLK =16000000; parameter IFFREQ =3780000 ; parameter CHIPRATE=2046000 ; //parameter GPSCHIPRATE_INCR = (1<<28)*CHIPRATE/SAMPCLK ; //parameter GPSIFFREQ_INCR = (1<<29)*IFFREQ/SAMPCLK ; reg [27:0] code_dco_incr; reg [28:0] code_dco_acc; reg code_dco_acc_msb_dly; wire next_ca_code; reg [1:0] count,count_dly; wire fc; reg [9:0] g2_load ; reg [9:0] g1_r ; reg [9:0] g2_r ; wire ca_code ; reg [9:0] dump_count; wire dump; reg [28:0] carr_dco_incr; reg [29:0] carr_dco_acc ; reg [2:0] cos,sin; wire [2:0] out_GPSData; wire in_config; reg [5:0] mscounter ; wire NaviBitPulse; reg [27:0]gpschiprate_incr; reg [29:0]gpsiffreq_incr; reg [9:0]satallite_prn; reg d_oe;reg [31:0]d_out;reg [15:0]d_out16;//write the preset registers, which should be initialized before correlator start to runalways @(posedge in_clk or negedge in_Resetn) if(!in_Resetn) begin gpschiprate_incr <= 28'h0; gpsiffreq_incr <= 30'h0; satallite_prn <= 10'h0; code_dco_incr <= 28'b0; end else if (~csn & ~wrn) `ifdef G4_FPGA_16BIT begin if (sel) if (a[7:0] == 8'h00) gpschiprate_incr[15:0] <= d[15:0]; else if (a[7:0] == 8'h02) gpschiprate_incr[27:16] <= d[11:0]; else if (a[7:0] == 8'h04) gpsiffreq_incr[15:0] <= d[15:0]; else if (a[7:0] == 8'h06) gpsiffreq_incr[29:16] <= d[13:0]; else if (a[7:0] == 8'h08) begin satallite_prn[9:0] <= d[9:0]; code_dco_incr <= gpschiprate_incr; end end `else begin if (sel) if (a[7:0] == 8'h00) gpschiprate_incr<= d[27:0]; else if (a[7:0] == 8'h04) gpsiffreq_incr <= d[27:0]; else if (a[7:0] == 8'h08) begin satallite_prn[9:0] <= d[9:0]; code_dco_incr <= gpschiprate_incr; end end `endif// register read operationsalways @(posedge in_clk or negedge in_Resetn) if(!in_Resetn) begin d_oe <= 1'b0; d_out <= 32'b0; d_out16<=16'b0; end else if (~csn & ~oen) `ifdef G4_FPGA_16BIT begin if (sel) d_oe <= 1'b1; if (a[7:0] == 8'h00) d_out16 <= gpschiprate_incr[15:0]; else if (a[7:0] == 8'h02) d_out16 <= {4'b0, gpschiprate_incr[27:16]}; else if (a[7:0] == 8'h04) d_out16 <= gpsiffreq_incr[15:0]; else if (a[7:0] == 8'h06) d_out16 <= {2'b0, gpsiffreq_incr[29:16]}; else if (a[7:0] == 8'h08) d_out16 <= {6'b0, satallite_prn}; else d_out16 <= 16'b0; end `else begin if (sel) d_oe <= 1'b1; d_out <= 0; if (a[7:0] == 8'h00) d_out[27:0] <= gpschiprate_incr; else if (a[7:0] == 8'h04) d_out[29:0] <= gpsiffreq_incr; else if (a[7:0] == 8'h08) d_out <= {22'b0, satallite_prn}; else d_out <= 32'b0; end `endif else d_oe <= 0; `ifdef G4_FPGA_16BITassign d = (d_oe) ? {16'b0,d_out16} : 32'hZZZZZZZZ;`else assign d = (d_oe) ? d_out : 32'hZZZZZZZZ;`endif //code dco assign in_config=1'b1; always @(posedge in_clk or negedge in_Resetn) if(!in_Resetn) code_dco_acc <= 29'b0; else code_dco_acc <= code_dco_acc + code_dco_incr; //delay the msb of code_dco_acc by 1 clock cycle for overflow generation always @(posedge in_clk or negedge in_Resetn) if(!in_Resetn) code_dco_acc_msb_dly <= 1'b0; else code_dco_acc_msb_dly <= code_dco_acc[28]; //if the msb of code_dco_acc changes during 1 cycle ,the out_next_ca_code is set assign next_ca_code = code_dco_acc_msb_dly ^ code_dco_acc[28]; //in_next_ca_code is 2fc,however g1 and g2 work at fc //so the following two always module and one assign generate fc //and the fc last for 1 in_clk cycle always @(posedge in_clk or negedge in_Resetn) if(!in_Resetn) count <= 2'b0; else if(next_ca_code) count <= count + 1'b1; always @(posedge in_clk or negedge in_Resetn) if(!in_Resetn) count_dly <= 2'b0; else count_dly <= count; assign fc = count[1] ^ (count_dly[1]); //g2_load is loaded from register file when config_valid is set always @ (posedge in_clk or negedge in_Resetn) if (!in_Resetn) g2_load <= 10'b0; else g2_load <= satallite_prn; //G1 register 1+x3+x10 always @(posedge in_clk or negedge in_Resetn) if(!in_Resetn) g1_r <= 10'h3ff; else if(fc) g1_r <= {g1_r[8:0],g1_r[2]^g1_r[9]}; //G2 register 1+x2+x3+x6+x8+x9+x10 always @(posedge in_clk or negedge in_Resetn) if(!in_Resetn) g2_r <= 10'h3ff; else if(fc) g2_r <= {g2_r[8:0],g2_r[1]^g2_r[2]^g2_r[5]^g2_r[7]^g2_r[8]^g2_r[9]}; //generate ca code assign ca_code = (^ (g2_load & g2_r)) ^ g1_r[9]; //generate dump signal //dump counter does not increase when slew always @(posedge in_clk or negedge in_Resetn) if(!in_Resetn) dump_count <= 10'b0; else if (dump) dump_count <= 0; else if(fc) dump_count <= dump_count + 1'b1; //when dump counter equal to 1023 dump signal is set //assign dump = (&(dump_count)) ? 1'b1 : 1'b0;assign dump = (dump_count == 'd1022)& fc; //ms counter 0-19 always @(posedge in_clk or negedge in_Resetn) if(!in_Resetn) mscounter <= 1'b0; else if ((mscounter == 19) & (dump) & fc) mscounter <= 1'b0; else if(dump & fc) mscounter <= mscounter + 1'b1; assign NaviBitPulse = ((mscounter == 19) & (dump) & fc)?1'b1:1'b0; assign o_NBPulse = NaviBitPulse; always @ (posedge in_clk or negedge in_Resetn) if (!in_Resetn) carr_dco_incr <= 29'b0; else carr_dco_incr <= gpsiffreq_incr; //acc increment carr_dco_incr every corrclk cycle always @(posedge in_clk or negedge in_Resetn ) if(!in_Resetn) carr_dco_acc <= 30'b0; else carr_dco_acc <= carr_dco_acc + carr_dco_incr; //make the sin map and cos map of bit[28:26] of carr_dco_acc //the sin and cos signal is coded in 2'complement and the msb is sign and the 2 lsbs are magnitude //the map base on the table below: //carr_dco_acc[28:26] sin cos ?? 快捷鍵說明
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