;BWSCON
DW8			EQU	(0x0)
DW16		EQU	(0x1)
DW32		EQU	(0x2)
WAIT		EQU	(0x1<<2)
UBLB		EQU	(0x1<<3)

B1_BWSCON	EQU (DW32)
B2_BWSCON	EQU (DW16)
B3_BWSCON	EQU (DW16)
B4_BWSCON	EQU (DW16)
B5_BWSCON	EQU (DW16)
B6_BWSCON	EQU (DW32)
B7_BWSCON	EQU (DW32)

;BANK0CON 
B0_Tacs		EQU		0x0		;0clk
B0_Tcos		EQU		0x0		;0clk
B0_Tacc		EQU		0x7		;14clk
B0_Tcoh		EQU		0x0		;0clk
B0_Tah		EQU		0x0		;0clk
B0_Tacp		EQU		0x0
B0_PMC		EQU		0x0		;normal

;BANK1CON
B1_Tacs		EQU		0x0		;0clk
B1_Tcos		EQU		0x0		;0clk
B1_Tacc		EQU		0x7		;14clk
B1_Tcoh		EQU		0x0		;0clk
B1_Tah		EQU		0x0		;0clk
B1_Tacp		EQU		0x0	
B1_PMC		EQU		0x0		;normal

;Bank 2 parameter
B2_Tacs		EQU		0x0		;0clk
B2_Tcos		EQU		0x0		;0clk
B2_Tacc		EQU		0x7		;14clk
B2_Tcoh		EQU		0x0		;0clk
B2_Tah		EQU		0x0		;0clk
B2_Tacp		EQU		0x0	
B2_PMC		EQU		0x0		;normal

;Bank 3 parameter
B3_Tacs		EQU		0x0		;0clk
B3_Tcos		EQU		0x0		;0clk
B3_Tacc		EQU		0x7		;14clk
B3_Tcoh		EQU		0x0		;0clk
B3_Tah		EQU		0x0		;0clk
B3_Tacp		EQU		0x0	
B3_PMC		EQU		0x0		;normal

;Bank 4 parameter
B4_Tacs		EQU		0x0		;0clk
B4_Tcos		EQU		0x0		;0clk
B4_Tacc		EQU		0x7		;14clk
B4_Tcoh		EQU		0x0		;0clk
B4_Tah		EQU		0x0		;0clk
B4_Tacp		EQU		0x0	
B4_PMC		EQU		0x0		;normal

;Bank 5 parameter
B5_Tacs		EQU		0x0		;0clk
B5_Tcos		EQU		0x0		;0clk
B5_Tacc		EQU		0x7		;14clk
B5_Tcoh		EQU		0x0		;0clk
B5_Tah		EQU		0x0		;0clk
B5_Tacp		EQU		0x0	
B5_PMC		EQU		0x0		;normal

;Bank 6 parameter
B6_MT		EQU		0x3		;SDRAM
B6_Trcd		EQU		0x1		;3clk
B6_SCAN		EQU		0x1		;9bit

;Bank 7 parameter
B7_MT		EQU		0x3		;SDRAM
B7_Trcd		EQU		0x1		;3clk
B7_SCAN		EQU		0x1		;9bit

;REFRESH parameter
REFEN		EQU		0x1		;Refresh enable
TREFMD		EQU		0x0		;CBR(CAS before RAS)/Auto refresh
Trp			EQU		0x0		;2clk
Tsrc		EQU		0x1		;5clk
;//REFCNT		EQU		480
REFCNT		EQU		1113
;//REFCNT		EQU		1269	;period=15.6us, HCLK=50Mhz, (2048+1-15.6*50)

; Flexible bank size register
BURST_EN	EQU		0		; ARM core burst operation enable.
SCKE_EN		EQU		1		; SDRAM power down mode enable control by SCKE
SCLK_EN		EQU		1		; SCLK is enabled only during SDRAM access cycle for reducing power consumption. When SDRAM is not accessed,
BK76MAP		EQU		2		; 128MB/128MB

; Mode register set register bank6
B6_WBL		EQU		0		; Burst (Fixed)
B6_TM		EQU		0		; Mode register set (Fixed)
B6_CL		EQU		3		; CAS latency
B6_BT		EQU		0		; 0: Sequential (Fixed)
B6_BL		EQU		0		; Burst length

; Mode register set register bank7
B7_WBL		EQU		0		; Burst (Fixed)
B7_TM		EQU		0		; Mode register set (Fixed)
B7_CL		EQU		3		; CAS latency
B7_BT		EQU		0		; 0: Sequential (Fixed)
B7_BL		EQU		0		; Burst length

	EXPORT	MemCFG

	AREA	_MemCFG,CODE,READONLY
	CODE32
MemCFG
	DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
	DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ;GCS0
	DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ;GCS1 
	DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ;GCS2
	DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ;GCS3
	DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ;GCS4
	DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ;GCS5
	DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))														;GCS6
	DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))														;GCS7
	DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+REFCNT)
	DCD ((BURST_EN<<7)+(SCKE_EN<<5)+(SCLK_EN<<4)+(BK76MAP))
	DCD	((B6_WBL<<9)+(B6_TM<<7)+(B6_CL<<4)+(B6_BT<<3)+(B6_BL))
	DCD	((B7_WBL<<9)+(B7_TM<<7)+(B7_CL<<4)+(B7_BT<<3)+(B7_BL))

	END