?? uart_test_srr.htm
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<!@TC:1219108136>
#Build: Synplify Pro 9.0.2A2, Build 250R, Feb 20 2008
#install: D:\Libero\Synplify\synplify_902A2
#OS: Windows XP 5.1
#Hostname: BIMINGMING
#Implementation: synthesis
#Tue Aug 19 09:08:56 2008
<a name=compilerReport1>$ Start of Compile
#Tue Aug 19 09:08:56 2008
Synplicity Verilog Compiler, version 1.0, Build 145R, built Mar 5 2008
Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved
@I::"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v"
@I::"E:\programer_new\UART\project\hdl\rec.v"
@I::"E:\programer_new\UART\project\hdl\send.v"
@I::"E:\programer_new\UART\project\hdl\uart_test.v"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module uart_test
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="E:\programer_new\UART\project\hdl\rec.v:20:7:20:10:@N:CG364:@XP_MSG">rec.v(20)</a><!@TM:1219108136> | Synthesizing module rec
<font color=#A52A2A>@W:<a href="@W:CL170:@XP_HELP">CL170</a> : <a href="E:\programer_new\UART\project\hdl\rec.v:74:0:74:6:@W:CL170:@XP_MSG">rec.v(74)</a><!@TM:1219108136> | Pruning bit <9> of UartBuff[9:0] - not in use ...</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="E:\programer_new\UART\project\hdl\send.v:20:7:20:11:@N:CG364:@XP_MSG">send.v(20)</a><!@TM:1219108136> | Synthesizing module send
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="E:\programer_new\UART\project\hdl\send.v:36:22:36:32:@W:CG133:@XP_MSG">send.v(36)</a><!@TM:1219108136> | No assignment to datainbuf2</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="E:\programer_new\UART\project\hdl\uart_test.v:20:7:20:16:@N:CG364:@XP_MSG">uart_test.v(20)</a><!@TM:1219108136> | Synthesizing module uart_test
<font color=#A52A2A>@W:<a href="@W:CS148:@XP_HELP">CS148</a> : <a href="E:\programer_new\UART\project\hdl\uart_test.v:57:6:57:13:@W:CS148:@XP_MSG">uart_test.v(57)</a><!@TM:1219108136> | Undriven input rst, tying to 0</font>
<font color=#A52A2A>@W:<a href="@W:CS148:@XP_HELP">CS148</a> : <a href="E:\programer_new\UART\project\hdl\uart_test.v:65:7:65:15:@W:CS148:@XP_MSG">uart_test.v(65)</a><!@TM:1219108136> | Undriven input rst, tying to 0</font>
<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="E:\programer_new\UART\project\hdl\uart_test.v:35:9:35:16:@W:CG360:@XP_MSG">uart_test.v(35)</a><!@TM:1219108136> | No assignment to wire clk100M</font>
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="E:\programer_new\UART\project\hdl\send.v:67:0:67:6:@W:CL189:@XP_MSG">send.v(67)</a><!@TM:1219108136> | Register bit datainbuf[0] is always 0, optimizing ...</font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\programer_new\UART\project\hdl\send.v:67:0:67:6:@W:CL171:@XP_MSG">send.v(67)</a><!@TM:1219108136> | Pruning Register bit <0> of datainbuf[9:0] </font>
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Aug 19 09:08:56 2008
###########################################################]
Synplicity Proasic Technology Mapper, Version 9.0.2, Build 065R, Built Mar 5 2008 17:44:07
Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved
Product Version Version 9.0.2A2
@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1219108136> | Running in 32-bit mode.
@N:<a href="@N:MF258:@XP_HELP">MF258</a> : <!@TM:1219108136> | Gated clock conversion disabled
RTL optimization done.
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 41MB)
@N:<a href="@N:MF238:@XP_HELP">MF238</a> : <a href="e:\programer_new\uart\project\hdl\uart_test.v:54:16:54:29:@N:MF238:@XP_MSG">uart_test.v(54)</a><!@TM:1219108136> | Found 8 bit incrementor, 'senddata_1[7:0]'
@N: : <a href="e:\programer_new\uart\project\hdl\rec.v:74:0:74:6:@N::@XP_MSG">rec.v(74)</a><!@TM:1219108136> | Found counter in view:work.rec(verilog) inst count_bit[3:0]
@N: : <a href="e:\programer_new\uart\project\hdl\rec.v:74:0:74:6:@N::@XP_MSG">rec.v(74)</a><!@TM:1219108136> | Found counter in view:work.rec(verilog) inst count[3:0]
@N: : <a href="e:\programer_new\uart\project\hdl\rec.v:49:0:49:6:@N::@XP_MSG">rec.v(49)</a><!@TM:1219108136> | Found counter in view:work.rec(verilog) inst cnt[15:0]
@N: : <a href="e:\programer_new\uart\project\hdl\send.v:90:0:90:6:@N::@XP_MSG">send.v(90)</a><!@TM:1219108136> | Found counter in view:work.send(verilog) inst bincnt[3:0]
@N: : <a href="e:\programer_new\uart\project\hdl\send.v:49:0:49:6:@N::@XP_MSG">send.v(49)</a><!@TM:1219108136> | Found counter in view:work.send(verilog) inst cnt[15:0]
Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 40MB peak: 41MB)
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 40MB peak: 41MB)
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 40MB peak: 42MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)
Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 42MB peak: 42MB)
Promoting Net clock_c on CLKBUF clock_pad
Buffering clksend, fanout 20 segments 2
Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)
Added 1 Buffers
Added 0 Cells via replication
Added 0 Sequential Cells via replication
Added 0 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)
Writing Analyst data base E:\programer_new\UART\project\synthesis\uart_test.srm
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1219108136> | Writing default property annotation file E:\programer_new\UART\project\synthesis\uart_test.map.
Writing EDIF Netlist and constraint files
Version 9.0.2A2
Found clock uart_test|clock with period 10.00ns
Found clock rec|RI_inferred_clock with period 10.00ns
Found clock send|clkout_inferred_clock with period 10.00ns
<a name=timingReport2>##### START OF TIMING REPORT #####[
# Timing Report written on Tue Aug 19 09:09:01 2008
#
Top view: uart_test
Library name: PA3
Operating conditions: COMWC-2 ( T = 70.0, V = 1.42, P = 1.30, tree_type = balanced_tree )
Requested Frequency: 100.0 MHz
Wire load mode: top
Wire load model: proasic3
Paths requested: 5
Constraint File(s):
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1219108141> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1219108141> | Clock constraints cover only FF-to-FF paths associated with the clock..
<a name=performanceSummary3>Performance Summary
*******************
Worst slack in design: 1.886
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------------------
send|clkout_inferred_clock 100.0 MHz 789.4 MHz 10.000 1.267 8.733 inferred Inferred_clkgroup_2
uart_test|clock 100.0 MHz 123.2 MHz 10.000 8.114 1.886 inferred Inferred_clkgroup_1
=================================================================================================================================
<a name=clockRelationships4>Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------------------------------------
rec|RI_inferred_clock uart_test|clock | Diff grp - | No paths - | No paths - | No paths -
uart_test|clock rec|RI_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
uart_test|clock uart_test|clock | 10.000 1.886 | No paths - | No paths - | No paths -
uart_test|clock send|clkout_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
send|clkout_inferred_clock uart_test|clock | Diff grp - | No paths - | No paths - | No paths -
send|clkout_inferred_clock send|clkout_inferred_clock | 10.000 8.733 | No paths - | No paths - | No paths -
==============================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
<a name=interfaceInfo5>Interface Information
*********************
No IO constraint found
====================================
<a name=clockReport6>Detailed Report for Clock: send|clkout_inferred_clock
====================================
<a name=startingSlack7>Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
WR_R1 send|clkout_inferred_clock DFN1 Q WR_R1 0.550 8.733
WR_R2 send|clkout_inferred_clock DFN1 Q WR_R2 0.550 8.733
========================================================================================
<a name=endingSlack8>Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------
WR_R2 send|clkout_inferred_clock DFN1 D WR_R1 9.572 8.733
WR_R3 send|clkout_inferred_clock DFN1 D WR_R2 9.572 8.733
=========================================================================================
<a name=worstPaths9>Worst Path Information
<a href="E:\programer_new\UART\project\synthesis\uart_test.srr:fp:10588:10825:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************
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