#-- Synplicity, Inc.
#-- Version 9.0
#-- Project file E:\programer_new\UART\project\synthesis\run_options.txt
#-- Written on Tue Aug 19 09:08:56 2008


#add_file options
add_file -verilog "E:/programer_new/UART/project/hdl/rec.v"
add_file -verilog "E:/programer_new/UART/project/hdl/send.v"
add_file -verilog "E:/programer_new/UART/project/hdl/uart_test.v"


#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology ProASIC3
set_option -part A3P030
set_option -speed_grade -2

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -top_module "uart_test"

#map options
set_option -frequency 100.000
set_option -run_prop_extract 1
set_option -fanout_limit 12
set_option -globalthreshold 50
set_option -maxfan_hard 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 4000
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"
project -result_file "./uart_test.edn"
impl -active "synthesis"