#add_file options
add_file -verilog "E:/programer_new/UART/project/hdl/rec.v"
add_file -verilog "E:/programer_new/UART/project/hdl/send.v"
add_file -verilog "E:/programer_new/UART/project/hdl/uart_test.v"
set_option -top_module uart_test

#device options
set_option -technology ProASIC3
set_option -part A3P030

#compilation/mapping options
set_option -symbolic_fsm_compiler true

#compilation/mapping options
set_option -frequency 100.000

#simulation options
impl -active "synthesis"
project -result_file "E:/programer_new/UART/project/synthesis/uart_test.edn"