ENTITY instfetch ISPORT (aluout : IN bit_vector(7 downto 0);instinp : IN bit_vector(15 downto 0);branch : IN BIT;reset1 : IN BIT;clock1 : IN BIT;irout : OUT bit_vector(15 downto 0);pcout : OUT bit_vector(7 downto 0));END instfetch;ARCHITECTURE instfetch_arch OF instfetch ISCOMPONENT pcPORT (Din2 : IN bit_vector(7 downto 0);clk2 : IN BIT;enable2 : IN BIT;resetpc : IN BIT;Dout2 : OUT bit_vector(7 downto 0));END COMPONENT ;COMPONENT instreg PORT (Din1 : IN bit_vector(15 downto 0);clk1 : IN BIT;enable1 : IN BIT;resetir : IN BIT;Dout1 : OUT bit_vector(15 downto 0));END COMPONENT ;COMPONENT instmem PORT (instsel : IN bit_vector(7 downto 0);instfake : IN bit_vector(15 downto 0);clk3 : IN BIT;instout : OUT bit_vector(15 downto 0));END COMPONENT;COMPONENT cla PORT (a : IN bit_vector(7 downto 0);b : IN bit_vector(7 downto 0);c0 : IN BIT;s : OUT bit_vector(7 downto 0);cout : OUT BIT);END COMPONENT ;COMPONENT mux2to1PORT (inp1 : IN BIT;inp2 : IN BIT;en : IN BIT;outp : OUT BIT);END COMPONENT;COMPONENT increment PORT (incinp : IN BIT;incout : OUT bit_vector(7 downto 0));END COMPONENT ;COMPONENT buffer0PORT (bo1 : IN BIT;bo2 : OUT BIT);END COMPONENT;COMPONENT buffer1 PORT (bu1 : IN BIT;bu2 : OUT BIT);END COMPONENT;COMPONENT bitreg PORT (bitin : IN BIT;clk3 : IN BIT;enable3 : IN BIT;bitout : OUT BIT);END COMPONENT;COMPONENT forwardtoout PORT (inputvector : IN bit_vector(7 downto 0);outputvector : OUT bit_vector(7 downto 0));END COMPONENT;SIGNAL carry1 : BIT;SIGNAL zerosig : BIT;SIGNAL onesig : BIT;SIGNAL mux1out : BIT_VECTOR(7 downto 0);SIGNAL pcstartout : BIT_VECTOR(7 downto 0);SIGNAL incsignal : BIT_VECTOR(7 downto 0);SIGNAL addout : BIT_VECTOR(7 downto 0);SIGNAL instout : BIT_VECTOR(15 downto 0);BEGINpc_start: pc PORT MAP(mux1out,clock1,onesig,reset1,pcstartout);--buffers dont operate on aluout(0)..some bit input is needed so this is used...buffer0_1 : buffer0 PORT MAP(clock1,zerosig);buffer1_1 : buffer1 PORT MAP(clock1,onesig);increment : increment PORT MAP(zerosig,incsignal);cla : cla PORT MAP(pcstartout,incsignal,zerosig,addout,carry1);mux2to1_1 : mux2to1 PORT MAP(addout(0),aluout(0),branch,mux1out(0));mux2to1_2 : mux2to1 PORT MAP(addout(1),aluout(1),branch,mux1out(1));mux2to1_3 : mux2to1 PORT MAP(addout(2),aluout(2),branch,mux1out(2));mux2to1_4 : mux2to1 PORT MAP(addout(3),aluout(3),branch,mux1out(3));mux2to1_5 : mux2to1 PORT MAP(addout(4),aluout(4),branch,mux1out(4));mux2to1_6 : mux2to1 PORT MAP(addout(5),aluout(5),branch,mux1out(5));mux2to1_7 : mux2to1 PORT MAP(addout(6),aluout(6),branch,mux1out(6));mux2to1_8 : mux2to1 PORT MAP(addout(7),aluout(7),branch,mux1out(7));pc1 : pc PORT MAP(mux1out,clock1,onesig,reset1,pcout);instmem : instmem PORT MAP(pcstartout,instinp,clock1,instout);instreg114 : instreg PORT MAP(instout,clock1,onesig,reset1,irout);END;