?? at91sam9xe128.h
字號(hào):
#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15
// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------
#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit
#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle
#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle
// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------
#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations
#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features
#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH
#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN
#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status
// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type
#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode
#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Static Memory Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SMC {
AT91_REG SMC_SETUP0; // Setup Register for CS 0
AT91_REG SMC_PULSE0; // Pulse Register for CS 0
AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
AT91_REG SMC_CTRL0; // Control Register for CS 0
AT91_REG SMC_SETUP1; // Setup Register for CS 1
AT91_REG SMC_PULSE1; // Pulse Register for CS 1
AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
AT91_REG SMC_CTRL1; // Control Register for CS 1
AT91_REG SMC_SETUP2; // Setup Register for CS 2
AT91_REG SMC_PULSE2; // Pulse Register for CS 2
AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
AT91_REG SMC_CTRL2; // Control Register for CS 2
AT91_REG SMC_SETUP3; // Setup Register for CS 3
AT91_REG SMC_PULSE3; // Pulse Register for CS 3
AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
AT91_REG SMC_CTRL3; // Control Register for CS 3
AT91_REG SMC_SETUP4; // Setup Register for CS 4
AT91_REG SMC_PULSE4; // Pulse Register for CS 4
AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
AT91_REG SMC_CTRL4; // Control Register for CS 4
AT91_REG SMC_SETUP5; // Setup Register for CS 5
AT91_REG SMC_PULSE5; // Pulse Register for CS 5
AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
AT91_REG SMC_CTRL5; // Control Register for CS 5
AT91_REG SMC_SETUP6; // Setup Register for CS 6
AT91_REG SMC_PULSE6; // Pulse Register for CS 6
AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
AT91_REG SMC_CTRL6; // Control Register for CS 6
AT91_REG SMC_SETUP7; // Setup Register for CS 7
AT91_REG SMC_PULSE7; // Pulse Register for CS 7
AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
AT91_REG SMC_CTRL7; // Control Register for CS 7
} AT91S_SMC, *AT91PS_SMC;
#else
#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0
#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0
#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0
#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0
#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1
#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1
#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1
#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1
#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2
#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2
#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2
#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2
#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3
#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3
#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3
#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3
#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4
#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4
#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4
#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4
#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5
#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5
#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5
#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5
#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6
#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6
#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6
#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6
#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7
#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7
#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7
#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7
#endif
// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------
#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length
#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access
#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length
#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------
#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length
#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access
#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length
#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------
#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length
#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length
// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode
#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode
#define AT91C_SMC_NWAITM (0x3 << 4) // (SMC) NWAIT Mode
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 4) // (SMC) External NWAIT disabled.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 4) // (SMC) External NWAIT enabled in frozen mode.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 4) // (SMC) External NWAIT enabled in ready mode.
#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.
#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.
#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.
#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR AHB Matrix Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_MATRIX {
AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k)
AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom)
AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs)
AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)
AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge)
AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox)
AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k)
AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog)
AT91_REG Reserved0[8]; //
AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k)
AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom)
AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs)
AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)
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