?? at91sam9xe256.h
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// SOFTWARE API DEFINITION FOR Error Correction Code controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ECC {
AT91_REG ECC_CR; // ECC reset register
AT91_REG ECC_MR; // ECC Page size register
AT91_REG ECC_SR; // ECC Status register
AT91_REG ECC_PR; // ECC Parity register
AT91_REG ECC_NPR; // ECC Parity N register
AT91_REG Reserved0[58]; //
AT91_REG ECC_VR; // ECC Version register
} AT91S_ECC, *AT91PS_ECC;
#else
#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register
#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register
#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register
#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register
#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register
#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register
#endif
// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register --------
#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity
// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register --------
#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size
// -------- ECC_SR : (ECC Offset: 0x8) ECC status register --------
#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error
#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error
#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR
// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register --------
#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error
#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit
// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register --------
#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N
// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register --------
#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register
// *****************************************************************************
// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SDRAMC {
AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
} AT91S_SDRAMC, *AT91PS_SDRAMC;
#else
#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
#endif
// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode
#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode
#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access
#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access
#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh
#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register
#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode
// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter
// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits
#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits
#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits
#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits
#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits
#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits
#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits
#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks
#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks
#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks
#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency
#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles
#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles
#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width
#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus
#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus
#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles
#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7
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