?? at91sam9xe256.h
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AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge)
AT91_REG Reserved1[11]; //
AT91_REG MATRIX_PRAS0; // PRAS0 (ram0)
AT91_REG MATRIX_PRBS0; // PRBS0 (ram0)
AT91_REG MATRIX_PRAS1; // PRAS1 (ram1)
AT91_REG MATRIX_PRBS1; // PRBS1 (ram1)
AT91_REG MATRIX_PRAS2; // PRAS2 (ram2)
AT91_REG MATRIX_PRBS2; // PRBS2 (ram2)
AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs
AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs
AT91_REG MATRIX_PRAS4; // PRAS4 : ebi
AT91_REG MATRIX_PRBS4; // PRBS4 : ebi
AT91_REG Reserved2[22]; //
AT91_REG MATRIX_MRCR; // Master Remp Control Register
AT91_REG Reserved3[6]; //
AT91_REG MATRIX_EBI; // Slave 3 (ebi) Special Function Register
AT91_REG Reserved4[3]; //
AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register
AT91_REG Reserved5[51]; //
AT91_REG MATRIX_VERSION; // Version Register
} AT91S_MATRIX, *AT91PS_MATRIX;
#else
#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 (ram96k)
#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 (rom)
#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 (hperiphs)
#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 (ebi)
#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 (bridge)
#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 (mailbox)
#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 (ram16k)
#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 (teak_prog)
#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 (ram96k)
#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 (rom)
#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 (hperiphs)
#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 (ebi)
#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 (bridge)
#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0 (ram0)
#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0 (ram0)
#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1 (ram1)
#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1 (ram1)
#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2 (ram2)
#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2 (ram2)
#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3 : usb_dev_hs
#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3 : usb_dev_hs
#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4 : ebi
#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4 : ebi
#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register
#define MATRIX_EBI (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_EBI) Slave 3 (ebi) Special Function Register
#define MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_TEAKCFG) Slave 7 (teak_prog) Special Function Register
#define MATRIX_VERSION (AT91_CAST(AT91_REG *) 0x000001FC) // (MATRIX_VERSION) Version Register
#endif
// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 --------
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 --------
#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 --------
#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 --------
#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 --------
#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register --------
#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority
#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority
#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority
#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority
#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority
#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority
#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority
#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority
// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register --------
#define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority
// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register --------
// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register --------
// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register --------
// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register --------
// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register --------
// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register --------
// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register --------
// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register --------
// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register --------
#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master
#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master
// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register --------
#define AT91C_MATRIX_CS1A (0x1 << 1) // (MATRIX) Chip Select 1 Assignment
#define AT91C_MATRIX_CS1A_SMC (0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
#define AT91C_MATRIX_CS1A_SDRAMC (0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
#define AT91C_MATRIX_CS3A (0x1 << 3) // (MATRIX) Chip Select 3 Assignment
#define AT91C_MATRIX_CS3A_SMC (0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
#define AT91C_MATRIX_CS3A_SM (0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
#define AT91C_MATRIX_CS4A (0x1 << 4) // (MATRIX) Chip Select 4 Assignment
#define AT91C_MATRIX_CS4A_SMC (0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
#define AT91C_MATRIX_CS4A_CF (0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
#define AT91C_MATRIX_CS5A (0x1 << 5) // (MATRIX) Chip Select 5 Assignment
#define AT91C_MATRIX_CS5A_SMC (0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
#define AT91C_MATRIX_CS5A_CF (0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
#define AT91C_MATRIX_DBPUC (0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration
// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register --------
#define AT91C_TEAK_PROGRAM_ACCESS (0x1 << 0) // (MATRIX) TEAK program memory access from AHB
#define AT91C_TEAK_PROGRAM_ACCESS_DISABLED (0x0) // (MATRIX) TEAK program access disabled
#define AT91C_TEAK_PROGRAM_ACCESS_ENABLED (0x1) // (MATRIX) TEAK program access enabled
#define AT91C_TEAK_BOOT (0x1 << 1) // (MATRIX) TEAK program start from boot routine
#define AT91C_TEAK_BOOT_DISABLED (0x0 << 1) // (MATRIX) TEAK program starts from boot routine disabled
#define AT91C_TEAK_BOOT_ENABLED (0x1 << 1) // (MATRIX) TEAK program starts from boot routine enabled
#define AT91C_TEAK_NRESET (0x1 << 2) // (MATRIX) active low TEAK reset
#define AT91C_TEAK_NRESET_ENABLED (0x0 << 2) // (MATRIX) active low TEAK reset enabled
#define AT91C_TEAK_NRESET_DISABLED (0x1 << 2) // (MATRIX) active low TEAK reset disabled
#define AT91C_TEAK_LVECTORP (0x3FFFF << 14) // (MATRIX) boot routine start address
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Chip Configuration Registers
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_CCFG {
AT91_REG Reserved0[3]; //
AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register
AT91_REG Reserved1[55]; //
AT91_REG CCFG_MATRIXVERSION; // Version Register
} AT91S_CCFG, *AT91PS_CCFG;
#else
#define CCFG_EBICSA (AT91_CAST(AT91_REG *) 0x0000000C) // (CCFG_EBICSA) EBI Chip Select Assignement Register
#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register
#endif
// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register --------
#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment
#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment
#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment
#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment
#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration
#define AT91C_EBI_SUPPLY (0x1 << 16) // (CCFG) EBI supply selection
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
AT91_REG PDC_RNPR; // Receive Next Pointer Register
AT91_REG PDC_RNCR; // Receive Next Counter Register
AT91_REG PDC_TNPR; // Transmit Next Pointer Register
AT91_REG PDC_TNCR; // Transmit Next Counter Register
AT91_REG PDC_PTCR; // PDC Transfer Control Register
AT91_REG PDC_PTSR; // PDC Transfer Status Register
} AT91S_PDC, *AT91PS_PDC;
#else
#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
#define PDC_TCR (AT91_CAST?? 快捷鍵說(shuō)明
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