/***********************************************************************
 file ID                    	:CPU_arm.asm
 Version Number           	:
 Project Code                	:
 Project Name               	:
 Architect    			:ProjectLeader
 Designer     			:
 Author                     	:  
 Date of last updation     	:02-04-2009
 Description             	: 

************************************************************************/
/*------------------------------ EQUATES--------------------------------------*/
OS_CPU_ARM_CONTROL_INT_DIS        EQU  0xC0                     ; Disable both FIQ and IRQ.
OS_CPU_ARM_CONTROL_FIQ_DIS        EQU  0x40                     ; Disable FIQ.
OS_CPU_ARM_CONTROL_IRQ_DIS        EQU  0x80                     ; Disable IRQ.
OS_CPU_ARM_CONTROL_THUMB          EQU  0x20                     ; Set THUMB mode.
OS_CPU_ARM_CONTROL_ARM            EQU  0x00                     ; Set ARM mode.

OS_CPU_ARM_MODE_MASK              EQU  0x1F
OS_CPU_ARM_MODE_USR               EQU  0x10
OS_CPU_ARM_MODE_FIQ               EQU  0x11
OS_CPU_ARM_MODE_IRQ               EQU  0x12
OS_CPU_ARM_MODE_SVC               EQU  0x13
OS_CPU_ARM_MODE_ABT               EQU  0x17
OS_CPU_ARM_MODE_UND               EQU  0x1B
OS_CPU_ARM_MODE_SYS               EQU  0x1F

OS_CPU_ARM_EXCEPT_RESET           EQU  0x00
OS_CPU_ARM_EXCEPT_UNDEF_INSTR     EQU  0x01
OS_CPU_ARM_EXCEPT_SWI             EQU  0x02
OS_CPU_ARM_EXCEPT_PREFETCH_ABORT  EQU  0x03
OS_CPU_ARM_EXCEPT_DATA_ABORT      EQU  0x04
OS_CPU_ARM_EXCEPT_ADDR_ABORT      EQU  0x05
OS_CPU_ARM_EXCEPT_IRQ             EQU  0x06
OS_CPU_ARM_EXCEPT_FIQ             EQU  0x07
/*----------------------------------- PUBLIC FUNCTIONS -----------------------*/
    PUBLIC  ARM_ExceptUndefInstrHndlr
    PUBLIC  ARM_ExceptSwiHndlr
    PUBLIC  ARM_ExceptPrefetchAbortHndlr
    PUBLIC  ARM_ExceptDataAbortHndlr
    PUBLIC  ARM_ExceptAddrAbortHndlr
    PUBLIC  ARM_ExceptIrqHndlr
    PUBLIC  ARM_ExceptFiqHndlr
    
    PUBLIC  CPU_SR_INT_Dis
    PUBLIC  CPU_SR_INT_En
        
    EXTERN  my_irq_handler
/*--------------------------CODE GENERATION DIRECTIVES------------------------*/

     RSEG CODE:CODE:NOROOT(2)
     CODE32
/*----------------------module for ENABLE INTERRUPTS--------------------------*/
CPU_SR_INT_En
    MRS     R0, CPSR
    BIC     R0, R0, #OS_CPU_ARM_CONTROL_INT_DIS                 ; Clear IRQ and FIQ bits in CPSR to enable all interrupts.
    MSR     CPSR_c, R0
    BX      LR
/*------------------------------ DISABLE INTERRUPTS---------------------------*/
CPU_SR_INT_Dis
    MRS     R0, CPSR
    ORR     R0, R0, #OS_CPU_ARM_CONTROL_INT_DIS                 ; Set IRQ and FIQ bits in CPSR to disable all interrupts.
    MSR     CPSR_c, R0
    BX      LR
    
/*---------------------------------------- EXCEPTION HANDLERS-----------------*/
/*-------------------------- UNDEFINED INSTRUCTION EXCEPTION HANDLER----------*/
ARM_ExceptUndefInstrHndlr
                                                                ; LR offset to return from this exception:  0.
    STMFD   SP!, {R0-R12, LR}                                   ; Push working registers.
    MOV     R2, LR                                              ; Save link register.
    MOV     R0, #OS_CPU_ARM_EXCEPT_UNDEF_INSTR                  ; Set exception ID to OS_CPU_ARM_EXCEPT_UNDEF_INSTR.
    B            ARM_ExceptHndlr                         ; Branch to global exception handler.

/*------------------SOFTWARE INTERRUPT EXCEPTION HANDLER-----------------------------------------*/
ARM_ExceptSwiHndlr
                                                                ; LR offset to return from this exception:  0.
    STMFD   SP!, {R0-R12, LR}                                   ; Push working registers.
    MOV     R2, LR                                              ; Save link register.
    MOV     R0, #OS_CPU_ARM_EXCEPT_SWI                          ; Set exception ID to OS_CPU_ARM_EXCEPT_SWI.
    B            ARM_ExceptHndlr                         ; Branch to global exception handler.
/*------------------------------PREFETCH ABORT EXCEPTION HANDLER--------------------------------*/
ARM_ExceptPrefetchAbortHndlr
    SUB     LR, LR, #4                                          ; LR offset to return from this exception: -4.
    STMFD   SP!, {R0-R12, LR}                                   ; Push working registers.
    MOV     R2, LR                                              ; Save link register.
    MOV     R0, #OS_CPU_ARM_EXCEPT_PREFETCH_ABORT               ; Set exception ID to OS_CPU_ARM_EXCEPT_PREFETCH_ABORT.
    B            ARM_ExceptHndlr                         ; Branch to global exception handler.

/*------------------------------DATA ABORT EXCEPTION HANDLER------------------------------------*/
ARM_ExceptDataAbortHndlr
    SUB     LR, LR, #8                                          ; LR offset to return from this exception: -8.
    STMFD   SP!, {R0-R12, LR}                                   ; Push working registers.
    MOV     R2, LR                                              ; Save link register.
    MOV     R0, #OS_CPU_ARM_EXCEPT_DATA_ABORT                   ; Set exception ID to OS_CPU_ARM_EXCEPT_DATA_ABORT.
    B            ARM_ExceptHndlr                         ; Branch to global exception handler.
/*------------------------------ADDRESS ABORT EXCEPTION HANDLER----------------------------------*/
ARM_ExceptAddrAbortHndlr
    SUB     LR, LR, #8                                          ; LR offset to return from this exception: -8.
    STMFD   SP!, {R0-R12, LR}                                   ; Push working registers.
    MOV     R2, LR                                              ; Save link register.
    MOV     R0, #OS_CPU_ARM_EXCEPT_ADDR_ABORT                   ; Set exception ID to OS_CPU_ARM_EXCEPT_ADDR_ABORT.
    B            ARM_ExceptHndlr                         ; Branch to global exception handler.
/*-------------------------------INTERRUPT REQUEST EXCEPTION HANDLER------------------------------*/
//OS_CPU_ARM_ExceptIrqHndlr
//    SUB     LR, LR, #4                                          ; LR offset to return from this exception: -4.
//    STMFD   SP!, {R0-R12, LR}                                   ; Push working registers.
//    B            OS_CPU_ARM_ExceptHndlr                         ; Branch to global exception handler.

ARM_ExceptIrqHndlr
    SUB     LR, LR, #4                                          ; LR offset to return from this exception: -4.
    STMFD   SP!, {R0-R12, LR}                                   ; Push working registers.
    MOV     R2, LR                                              ; Save link register.
    MOV     R0, #OS_CPU_ARM_EXCEPT_FIQ                          ; Set exception ID to OS_CPU_ARM_EXCEPT_FIQ.
    B            ARM_ExceptHndlr                         ; Branch to global exception handler.
/*------------------------------FAST INTERRUPT REQUEST EXCEPTION HANDLER--------------------------*/
ARM_ExceptFiqHndlr
    SUB     LR, LR, #4                                          ; LR offset to return from this exception: -4.
    STMFD   SP!, {R0-R12, LR}                                   ; Push working registers.
    MOV     R2, LR                                              ; Save link register.
    MOV     R0, #OS_CPU_ARM_EXCEPT_FIQ                          ; Set exception ID to OS_CPU_ARM_EXCEPT_FIQ.
    B            ARM_ExceptHndlr                         ; Branch to global exception handler.

/*----------------------------------GLOBAL EXCEPTION HANDLER--------------------------------------------*/

ARM_ExceptHndlr

    MRS     R1, SPSR                                            ; Save CPSR (i.e. exception's SPSR).

                                                                ; DETERMINE IF WE INTERRUPTED A TASK/IRQ OR ANOTHER LOWER PRIORITY EXCEPTION:
                                                                ;   SPSR.Mode = SVC                :  task or IRQ handled in SVC mode,
                                                                ;   SPSR.Mode = FIQ, IRQ, ABT, UND :  other exceptions,
                                                                ;   SPSR.Mode = USR                : *unsupported state*.
  //  AND     R3, R1, #OS_CPU_ARM_MODE_MASK
  //  CMP     R3,     #OS_CPU_ARM_MODE_SVC
    BNE     ARM_IRQ


/*-----------------------------------------------------------------------------*/
ARM_IRQ
    /*Handler implemented only for IRQ
      The handler does not support nested interrupt*/
    LDR     R3, =my_irq_handler                                 ; my_irq_handler
    MOV     LR, PC
    BX      R3 
    /* RESTORE OLD CONTEXT*/
    LDMFD   SP!, {R0-R12,PC}^
/*-----------------------------------------------------------------------------*/

   END