C51 COMPILER V6.10  SPI_CORE                                                               04/19/2001 11:47:53 PAGE 1   


C51 COMPILER V6.10, COMPILATION OF MODULE SPI_CORE
OBJECT MODULE PLACED IN .\Spi_core.OBJ
COMPILER INVOKED BY: C:\KEIL\C51\BIN\C51.EXE .\Spi_core.c BROWSE DEBUG OBJECTEXTEND

stmt level    source

   1          /*------------------------------------------------------------------*-
   2          
   3             SPI_Core.C (v1.00)
   4          
   5            ------------------------------------------------------------------
   6          
   7             Core SPI library for Atmel AT89S53.
   8          
   9          
  10             COPYRIGHT
  11             ---------
  12          
  13             This code is from the book:
  14          
  15             PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont 
  16             [Pearson Education, 2001; ISBN: 0-201-33138-1].
  17          
  18             This code is copyright (c) 2001 by Michael J. Pont.
  19           
  20             See book for copyright details and other information.
  21          
  22          -*------------------------------------------------------------------*/
  23          
  24          #include "Main.h"
  25          #include "Port.h"
  26          
  27          #include "SPI_Core.h"
  28          #include "TimeoutH.H"
  29          
  30          // ------ Public variable declarations -----------------------------
  31          
  32          // The error code variable
  33          //
  34          // See Main.C for port on which error codes are displayed
  35          // and for details of error codes
  36          extern tByte Error_code_G;
  37          
  38          /*------------------------------------------------------------------*-
  39          
  40            SPI_Init_AT89S53()
  41          
  42            Set up the on-chip SPI module.
  43          
  44          -*------------------------------------------------------------------*/
  45          void SPI_Init_AT89S53(const tByte SPI_MODE)
  46             {
  47   1         // SPI Control Register (SPCR)
  48   1         // Bit 7 = SPIE (enable SPI interrupt, if ES is also 1)
  49   1         // Bit 6 = SPE  (enable SPI)
  50   1         // Bit 5 = DORD (data order, 1 for LSB first, 0 for MSB first)
  51   1         // Bit 4 = MSTR (1 for master, 0 for slave)
  52   1         // Bit 3 = CPOL (clock polarity, 1 = high when idle, 0 = low when idle)
  53   1         // Bit 2 = CPHA (transfer format)
  54   1         // Bit 1 = SPR1 (SPR0, SPR1 control the clock rate)
  55   1         // Bit 0 = SPR0 
C51 COMPILER V6.10  SPI_CORE                                                               04/19/2001 11:47:53 PAGE 2   

  56   1         SPCR = SPI_MODE;
  57   1         }
  58          
  59          /*------------------------------------------------------------------*-
  60          
  61            SPI_Exchange_Bytes()
  62          
  63            Exchange a byte of data with the slave device.
  64          
  65          -*------------------------------------------------------------------*/
  66          tByte SPI_Exchange_Bytes(const tByte OUT)
  67             {
  68   1         // Write byte to SPI register (starts clock)
  69   1         // - these data will be transferred to the slave device
  70   1         SPDR = OUT;                  
  71   1      
  72   1         // Wait until byte transmitted with 5ms timeout - START 
  73   1      
  74   1         // Configure Timer 0 as a 16-bit timer for timeout
  75   1         TMOD &= 0xF0; // Clear all T0 bits (T1 left unchanged)
  76   1         TMOD |= 0x01; // Set required T0 bits (T1 left unchanged) 
  77   1      
  78   1         ET0 = 0;  // No interrupts
  79   1      
  80   1         // Simple timeout feature - approx 5ms
  81   1         TH0 = T_05ms_H; // See TimeoutH.H for T_ details
  82   1         TL0 = T_05ms_L;
  83   1         TF0 = 0; // Clear flag
  84   1         TR0 = 1; // Start timer
  85   1      
  86   1         while (((SPSR & SPIF_) == 0) && (!TF0)); 
  87   1      
  88   1         TR0 = 0;  
  89   1      
  90   1         if (TF0 == 1)
  91   1            {
  92   2            // SPI device timed out
  93   2            Error_code_G = ERROR_SPI_EXCHANGE_BYTES_TIMEOUT;
  94   2            }
  95   1      
  96   1         // Clear SPIF and WCOL
  97   1         SPSR &= 0x3F; 
  98   1      
  99   1         // Return contents of SPI register
 100   1         // - these are the data from the slave device               
 101   1         return SPDR;                 
 102   1         }
 103          
 104          /*------------------------------------------------------------------*-
 105            ---- END OF FILE -------------------------------------------------
 106          -*------------------------------------------------------------------*/
 107          


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =     45    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
C51 COMPILER V6.10  SPI_CORE                                                               04/19/2001 11:47:53 PAGE 3   

END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)