------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date:    12:14:17 05/26/2008 -- Design Name: -- Module Name:    cpu - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity cpu is    Port ( clk : in  STD_LOGIC;           reset : in  STD_LOGIC;           in_port : in  STD_LOGIC_VECTOR (7 downto 0);           out_port : out  STD_LOGIC_VECTOR (7 downto 0));end cpu;architecture Behavioral of cpu iscomponent ram32_b port(clk,en,we: in std_logic;		addr: in std_logic_vector(4 downto 0);		di: in std_logic_vector(7 downto 0);		do: out std_logic_vector(7 downto 0));end component;signal ir, a, di_ram, do_ram: std_logic_vector(7 downto 0);signal pc,addr_ram:std_logic_vector(4 downto 0);signal en_ram,we_ram:std_logic;type state_type is (start_s,fetch1_s,fetch2_s,decode_s,load1_s,load2_s,store_s,add1_s,add2_s,sub1_s,sub2_s,in_s,jz_s,jmp_s,halt_s);signal curr,nxt:state_type;beginu0:ram32_b port map(clk,en_ram,we_ram,addr_ram,di_ram,do_ram);process(clk,reset)beginif reset='1' then curr<=start_s;pc<="00000";a<=X"00";ir<=X"00";elsif (clk'event and clk='1') then curr<=nxt;end if;end process;process(curr)begincase curr iswhen start_s=>nxt<=fetch1_s;when fetch1_s=>nxt<=fetch2_s;en_ram<='1';we_ram<='0';addr_ram<=pc;when fetch2_s=>nxt<=decode_s;en_ram<='0';ir<=do_ram;pc<=pc+1;when decode_s=>	case ir(7 downto 5) is 	when "000" =>	nxt<=load1_s;	when "001" =>	nxt<=store_s;	when "010" =>	nxt<=add1_s;	when "011" =>	nxt<=sub1_s;	when "100" =>	nxt<=in_s;	when "101" =>	nxt<=jz_s;	when "110" =>	nxt<=jmp_s;	when others =>	nxt<=halt_s;end case;when load1_s =>en_ram<='1';we_ram<='0';addr_ram<=ir(4 downto 0);nxt<=load2_s;when load2_s =>en_ram<='0';a<=do_ram;nxt<=fetch1_s;when store_s =>en_ram<='1';we_ram<='1';addr_ram<=ir(4 downto 0);di_ram<=a;nxt<=fetch1_s;when add1_s =>en_ram<='1';addr_ram<=ir(4 downto 0);nxt<=add2_s;when add2_s =>en_ram<='0';a<=a+do_ram;nxt<=fetch1_s;when sub1_s =>en_ram<='1';addr_ram<=ir(4 downto 0);nxt<=sub2_s;when sub2_s =>en_ram<='0';a<=a-do_ram;nxt<=fetch1_s;when in_s =>a<=in_port;nxt<=fetch1_s;when jz_s =>if a=X"00" then pc<=ir(4 downto 0);end if;nxt<=fetch1_s;when jmp_s =>pc<=ir(4 downto 0);nxt<=fetch1_s;when halt_s =>nxt<=halt_s;end case;end process;end Behavioral;